When a power semiconductor gets hot, its electrical behavior changes. For silicon power MOSFETs, the resistance and temperature relationship is strictly positive: as the junction temperature rises, the on-resistance ($R_{DS(on)}$) increases. This creates a dangerous positive feedback loop where higher resistance leads to more $I^2R$ heating, which further increases resistance. To prevent thermal runaway, designers must manage the component's thermal resistance ($R_{\theta}$) just as carefully as its electrical resistance.
The Dual Resistance Problem: Electrical vs. Thermal
On the bench, we deal with two distinct types of resistance when sizing power stages. The first is electrical. Take the ubiquitous IRF3205 MOSFET. At a case temperature of 25°C, its $R_{DS(on)}$ is typically 8.0 mΩ. However, if the junction reaches 125°C, that resistance roughly doubles to 16.0 mΩ. If you are passing 20A through the device, your power dissipation jumps from 3.2W at room temperature to 6.4W when hot.
This electrical shift dictates the heat generated. The second resistance—thermal resistance ($R_{\theta}$)—dictates how efficiently that heat escapes into the surrounding air. Thermal resistance is measured in °C/W (degrees Celsius per watt). It acts exactly like electrical resistance in Ohm's Law, but instead of voltage drop, we calculate temperature rise:
Thermal Ohm's Law: $\Delta T = P_D \times R_{\theta}$
Where $\Delta T$ is the temperature rise, $P_D$ is power dissipated in watts, and $R_{\theta}$ is thermal resistance.
Ignoring the thermal path while only calculating electrical $I^2R$ losses at 25°C is the most common reason DIY motor controllers and power supplies melt down during summer testing. You must design for the hot-state electrical resistance, then build a thermal path to keep the junction below its limits.
Thermal Path Math and Derating Curves
To find the actual junction temperature ($T_J$), we sum the thermal resistances from the silicon die all the way to the room air. The complete thermal path equation is:
$T_J = T_A + P_D \times (R_{\theta JC} + R_{\theta CS} + R_{\theta SA})$
- $T_A$: Ambient temperature (inside the enclosure, not just the room).
- $R_{\theta JC}$: Junction-to-Case resistance (fixed by the manufacturer).
- $R_{\theta CS}$: Case-to-Sink resistance (determined by your thermal interface material).
- $R_{\theta SA}$: Sink-to-Ambient resistance (determined by your heatsink and airflow).
| Path Segment | Symbol | Value (°C/W) | Determining Factor |
|---|---|---|---|
| Junction-to-Case | $R_{\theta JC}$ | 1.0 | Silicon die size and TO-220 package copper tab |
| Case-to-Sink | $R_{\theta CS}$ | 0.5 | Thermal pad (e.g., Bergquist Sil-Pad 400VO) |
| Sink-to-Ambient | $R_{\theta SA}$ | 12.5 | Extruded aluminum heatsink profile |
| Total Thermal Resistance | $R_{\theta JA}$ | 14.0 | Sum of the series path |
Using our 6.4W dissipation and a 40°C ambient enclosure temperature, the junction temperature calculates to: $T_J = 40 + (6.4 \times 14.0) = 129.6°C$.
Interpreting the Derating Curve: How Hot is Too Hot?
Most MOSFET datasheets list an absolute maximum junction temperature ($T_{J(max)}$) of 175°C. However, operating at 175°C is a fast track to failure. The derating curve in the datasheet shows linear power derating starting at a 25°C case temperature, dropping to 0W at 175°C.
Heatsink Selection and Airflow Strategies
Continuing our IRF3205 example, we need a heatsink that keeps $T_J$ under 125°C in a 40°C enclosure. Rearranging the thermal equation to solve for the required $R_{\theta SA}$:
$R_{\theta SA} = ((T_{J(target)} - T_A) / P_D) - R_{\theta JC} - R_{\theta CS}$
$R_{\theta SA} = ((125 - 40) / 6.4) - 1.0 - 0.5 = 11.78°C/W$.
We need a heatsink with a thermal resistance of 11.78 °C/W or lower. A standard off-the-shelf choice is the Aavid Thermalloy 530602B02500G, a TO-220 extruded heatsink rated at 12.5 °C/W in natural convection. Wait—that is slightly higher than our 11.78 °C/W target. We have two choices: buy a larger, more expensive heatsink, or introduce forced airflow.
| Cooling Method | Airflow (LFM) | Effective $R_{\theta SA}$ | Resulting $T_J$ |
|---|---|---|---|
| Natural Convection | 0 (Still air) | 12.5 °C/W | 133.6°C (Too hot) |
| Low Forced Air | 100 LFM (~0.5 m/s) | 7.5 °C/W | 97.6°C (Safe margin) |
| High Forced Air | 400 LFM (~2.0 m/s) | 4.5 °C/W | 78.4°C (Excellent) |
Adding a basic 40mm x 10mm brushless fan (like a Noctua NF-A4x10) pushing just 100 LFM (Linear Feet per Minute) across the fins drops the effective thermal resistance by 40%.
What Enclosure Changes Buy You
If you cannot use a fan, you must alter the enclosure. Sealed plastic enclosures act as thermal insulators, causing $T_A$ to rise until thermal equilibrium is reached—often 20°C above room temperature. Cutting ventilation louvers at the bottom and top of the enclosure creates a chimney effect, leveraging natural convection to pull cool air over the Aavid heatsink fins. Alternatively, using the aluminum enclosure chassis itself as the heatsink (by mounting the TO-220 directly to the chassis wall with an insulating pad) can drop system $R_{\theta SA}$ to under 5 °C/W for large enclosures.
Failure Signatures of Thermal Stress
When the resistance and temperature relationship pushes a part beyond its thermal limits, the failure is rarely instantaneous. It leaves forensic evidence on the PCB:
- Gate Threshold Shift and Phantom Turn-On: As temperature spikes, the MOSFET's gate threshold voltage ($V_{GS(th)}$) drops (a negative temperature coefficient). In half-bridge circuits, this can cause the hot MOSFET to turn on spuriously from $dV/dt$ coupling, resulting in shoot-through and catastrophic failure.
- Solder Reflow and Flux Carbonization: If the TO-220 leads exceed 180°C locally, the PCB solder joints will soften. You will see the component leaning, or dark, carbonized flux residue pooling around the pins.
- Die Attach Delamination: Repeated thermal cycling (heating up under load, cooling down at idle) causes the silicon die and the copper tab to expand at different rates. This cracks the solder die-attach layer, creating a localized hot spot that eventually punches through the silicon.
For deeper analysis on component thermal limits, refer to the All About Circuits heatsink selection guide, which details the mechanical mounting pressures required to maintain low $R_{\theta CS}$ values.
FAQ: Resistance and Temperature Relationship Deep Dives
How does the resistance and temperature relationship trigger thermal runaway in parallel MOSFETs?
At high currents, the positive temperature coefficient (PTC) of $R_{DS(on)}$ actually helps parallel MOSFETs self-balance; if one gets hotter, its resistance rises, forcing current into the cooler sibling. However, at low currents and low gate drive voltages, the gate threshold voltage ($V_{GS(th)}$) dominates. $V_{GS(th)}$ has a negative temperature coefficient (dropping about -6mV/°C). If one MOSFET gets slightly warmer, its threshold drops, causing it to turn on harder and hog the low-level current. This can trigger low-current thermal runaway in linear mode or soft-switching applications. Always ensure adequate gate drive voltage (e.g., 10V-12V) to operate firmly in the PTC region.
What is the exact resistance and temperature relationship formula for PCB copper traces?
Copper also exhibits a positive temperature coefficient. When sizing traces using the IPC-2152 standard, you must account for the trace heating up and increasing its own resistance. The formula is:
$R_T = R_0 \times [1 + \alpha \times (T - T_0)]$
Where $R_0$ is the resistance at reference temperature $T_0$ (usually 20°C), and $\alpha$ is the temperature coefficient of copper, which is 0.00393 per °C. If a 1oz copper trace heats up by 50°C above ambient, its electrical resistance increases by nearly 20%, which in turn increases $I^2R$ heating. This is why internal PCB layers, which have worse thermal dissipation than external layers, require significantly wider traces for the same current.
How do NTC thermistors exploit the resistance and temperature relationship?
Negative Temperature Coefficient (NTC) thermistors are engineered from metal oxide ceramics to have a highly predictable, non-linear inverse resistance and temperature relationship. As they heat up, more charge carriers are excited across the semiconductor bandgap, causing resistance to plummet. The relationship is modeled using the Steinhart-Hart equation or the simpler Beta ($\beta$) parameter equation:
$R_T = R_{25} \times e^{\beta \times (\frac{1}{T} - \frac{1}{298.15})}$
Where $T$ is in Kelvin. A standard 10kΩ NTC (like the EPCOS B57891S0103) with a $\beta$ of 3988K will drop from 10,000Ω at 25°C to roughly 1,200Ω at 85°C. We use these specifically to monitor the heatsink temperature and feed that data back to a microcontroller to ramp up fan PWM duty cycles before the MOSFET junction reaches critical limits.
