Designing an RC Low-Pass Filter and Circuit Diagram for ESP32 PWM DAC

To convert a 5kHz PWM signal from an ESP32 into a stable, usable DC voltage, use a first-order RC low-pass filter configured with a 1kΩ series resistor and a 100nF C0G/NP0 shunt capacitor. This specific combination yields a 1.59kHz cutoff frequency, settles in under 2ms, and limits peak-to-peak ripple to roughly 40mV at a 50% duty cycle. Understanding how to draft this RC low-pass filter and circuit diagram is essential for creating cheap, highly effective digital-to-analog converters (DACs) without relying on dedicated, expensive DAC ICs.

Topology, Node Labels, and the Core Circuit Diagram

A first-order passive RC low-pass filter relies on the frequency-dependent impedance of a capacitor to shunt high-frequency AC components to ground while allowing the DC average to pass through to the load. When mapping out your RC low-pass filter and circuit diagram, the topology consists of exactly two passive components arranged in an L-shape.

The circuit is defined by three critical nodes:

• Node A (Vin): The PWM source. On an ESP32-WROOM-32, this is typically a GPIO pin driven by the hardware LEDC peripheral (e.g., GPIO 25), outputting a 0V to 3.3V square wave.
• Node B (Vout): The filter output. This is the electrical junction between the series resistor and the shunt capacitor. This node connects to your target analog load, such as an op-amp input, a motor driver control pin, or an ADC input for feedback.
• Node C (GND): The common ground reference shared by the ESP32, the capacitor, and the downstream load.

The physics governing this topology is straightforward: the resistor limits the current flow, while the capacitor stores charge. During the PWM high-state, the capacitor charges through the resistor; during the low-state, it discharges. If the RC time constant ($\tau = R \times C$) is significantly larger than the PWM period ($T = 1/f$), the voltage at Node B cannot swing fully to the rails, effectively averaging the square wave into a smooth DC level proportional to the duty cycle.

Component Selection and Behavior Matrix

Selecting the right resistor and capacitor values requires balancing three competing factors: ripple voltage (smoothness), settling time (responsiveness), and output impedance (drive capability). Below is a data-dense specification table detailing real-world component combinations for a 5kHz ESP32 PWM signal.

Behavior Table: What Changes When You Alter One Element?

When tuning your RC low-pass filter and circuit diagram, changing a single parameter cascades through the circuit's behavior. Use this matrix to predict the outcome of your tweaks.

Why a Passive RC Topology Over LC or Active Alternatives?

When drafting an analog output stage, engineers often debate between passive RC, passive LC, and active op-amp filters. For microcontroller PWM smoothing, the RC topology wins on practicality, but it is vital to understand the trade-offs.

Choose RC when: You are driving a high-impedance load (like an ADC input or an op-amp buffer), board space is at a premium, and you need a fast, cheap, guaranteed-stable solution without EMI risks.

Choose LC when: You need to pass high DC current to a low-impedance load (like a motor or LED string) where a series resistor would cause unacceptable voltage drop and thermal dissipation.

Choose Active when: Your load has a low input impedance that would drag down a passive RC filter's voltage, or when you require a steep roll-off (2nd or 3rd order) to eliminate high-frequency switching noise entirely.

Failure Mode Analysis: What Breaks at the Extremes?

A robust circuit design anticipates component failure. Because the RC filter is a simple series-parallel network, the failure modes are distinct and easily diagnosable with a multimeter. Here is the failure-mode contrast for the extremes:

• Shunt Capacitor (C) Shorts: Node B is pulled directly to GND. The output voltage drops to 0V. Crucial ESP32 context: The series resistor (R) now acts as the sole current limiter. If R is 1kΩ, the GPIO sources 3.3mA (safe). If R is 100Ω, the GPIO sources 33mA, which risks degrading the ESP32's internal silicon bond wires over time.
• Shunt Capacitor (C) Opens: The filtering action ceases entirely. Node B will output the raw, unfiltered 0-3.3V 5kHz square wave. A standard DC multimeter will read the average DC voltage (e.g., 1.65V at 50% duty), masking the fault unless you use an oscilloscope to check for AC ripple.
• Series Resistor (R) Shorts: Node B receives the raw PWM square wave directly from the GPIO pin. More dangerously, the ESP32 GPIO must now supply the instantaneous inrush current to charge the uncharged capacitor ($I = C \cdot \frac{dV}{dt}$). This current spike can easily exceed the 40mA absolute maximum rating of the ESP32 pin, potentially destroying the GPIO port.
• Series Resistor (R) Opens: Node B is disconnected from the source. The capacitor will hold its last charged voltage and slowly bleed off through the leakage current of the capacitor dielectric and the input impedance of whatever is connected to Vout (e.g., a 10MΩ oscilloscope probe).

Step-by-Step Breadboard Testing and Verification

Do not trust theoretical calculations blindly. Parasitic breadboard capacitance (typically 2pF to 5pF per node) and GPIO output impedance will slightly alter your results. Follow this verification sequence to validate your RC low-pass filter and circuit diagram in the physical world.

1. Flash the Test Firmware: Program your ESP32 using the hardware LEDC peripheral. Configure Timer 0 for 5kHz frequency and 10-bit resolution. Attach Channel 0 to GPIO 25. Set the duty cycle to 512 (exactly 50%). Consult the official Espressif LEDC API documentation for exact register configurations.
2. Insert the Passives: Place a 1kΩ 1/4W through-hole resistor and a 100nF C0G/NP0 ceramic capacitor on the breadboard. Connect GPIO 25 to one leg of the resistor. Connect the other leg of the resistor to one leg of the capacitor (this is Node B / Vout). Connect the other leg of the capacitor to the ESP32 GND rail.
3. Verify with a DMM: Set your digital multimeter to DC Volts. Probe Node B. You should read between 1.60V and 1.68V. If you read exactly 3.3V or 0V, check for breadboard contact failures or an open/shorted component.
4. Verify with an Oscilloscope: Connect your scope probe to Node B. Ensure the probe is set to 1X (or compensate if using 10X). Trigger on the rising edge. You should see a 'sawtooth' ripple centered around 1.65V. Measure the peak-to-peak voltage ($V_{pp}$). For a 1kΩ/100nF combo at 5kHz, expect a $V_{pp}$ ripple of approximately 35mV to 45mV. Review fundamental AC ripple calculations if your measured values deviate by more than 15%.
5. Test the Step Response: Change your firmware duty cycle from 512 (50%) to 1023 (100%) in a loop with a 1-second delay. Observe the scope. The voltage should rise exponentially, reaching 99% of 3.3V (approx 3.26V) in roughly 5 time constants ($5 \times 100\mu s = 500\mu s$ or 0.5ms). If the rise time is significantly slower, your capacitor value is larger than labeled, or you are using a high-ESR electrolytic capacitor.

By rigorously testing the physical circuit against the theoretical behavior matrix, you ensure your ESP32 PWM DAC will perform reliably under real-world load conditions, avoiding the common pitfalls of component tolerance and dielectric absorption.