The standard 1st-order RC low pass filter circuit diagram consists of a single series resistor and a shunt capacitor to ground. For 90% of microcontroller sensor inputs and basic ADC anti-aliasing tasks, an 820Ω resistor paired with a 100nF C0G/NP0 capacitor is the optimal default. This combination yields a -3dB cutoff frequency of 1.94 kHz while maintaining a low enough source impedance to properly charge the internal sampling capacitors of SAR ADCs like those found on the ESP32 or STM32.
The Core Decision: Passive RC vs. Active Topologies
Before laying out traces or plugging into a breadboard, you must choose the right topology. A passive RC filter is cheap and requires no power rails, but it suffers from load-dependent cutoff shifting and a gentle -20dB/decade roll-off. Active filters (using op-amps) or LC filters solve these issues but introduce complexity, noise, and board space penalties.
| Criteria | 1st-Order Passive RC | 2nd-Order Active (Sallen-Key) | Passive LC (Pi / T) |
|---|---|---|---|
| Roll-off Rate | -20 dB/decade | -40 dB/decade | -40 to -60 dB/decade |
| Load Sensitivity | High (cutoff shifts if load < 10x R) | None (buffered output) | Moderate to High |
| Power Requirement | None | Dual or single supply rails | None |
| Best Application | DC/Slow sensor ADC anti-aliasing | Audio, high-speed precision ADCs | RF interference, switching supplies |
1st-Order RC Low Pass Filter Circuit Diagram & Node Topology
The beauty of the passive RC low pass filter circuit diagram lies in its operation as a frequency-dependent voltage divider. The resistor provides a fixed impedance, while the capacitor provides a frequency-dependent reactance ($X_c = \frac{1}{2\pi fC}$). As frequency increases, the capacitor's impedance drops, shunting high-frequency noise to ground.
Node Labels and Signal Flow
- Node 1 (Vin): The raw input signal. This connects to the lead of the series resistor.
- Node 2 (Vout / Node A): The junction between the resistor and the capacitor. This is your filtered output. It connects to the ADC input or next stage.
- Node 3 (GND): The ground reference. The second lead of the capacitor connects here, completing the shunt path.
At DC (0 Hz), the capacitor acts as an open circuit. Node 2 sees the full DC voltage of Node 1 (minus any negligible DC drop across the resistor caused by the load's leakage current). At very high frequencies, the capacitor acts as a short circuit, pulling Node 2 to 0V (GND).
Component Behavior & Extreme Failure Modes
Understanding how component drift or catastrophic failure affects the circuit is critical for debugging. A filter that fails "open" might pass destructive high-frequency noise into a sensitive ADC, while a filter that fails "short" will kill your signal entirely.
Parameter Drift Behavior Table
| Change | Effect on Cutoff Frequency ($f_c$) | Effect on Signal Integrity |
|---|---|---|
| R increases | $f_c$ decreases (filter gets slower) | Increases thermal (Johnson-Nyquist) noise; risks ADC sampling errors due to high source impedance. |
| C increases | $f_c$ decreases (filter gets slower) | Larger physical size; higher risk of microphonic noise and dielectric absorption if using X7R ceramics. |
| Load Z decreases | $f_c$ increases (filter gets faster) | Severe signal attenuation. The load forms a parallel resistance with the capacitor, ruining the -3dB point. |
Extreme Failure Mode Contrast
| Component | Failure Mode | Circuit Result | System Consequence |
|---|---|---|---|
| Resistor | Open | Vout = 0V (floating/grounded via C) | Total signal loss; ADC reads 0 or floats randomly. |
| Resistor | Short | Vout = Vin (filter bypassed) | Full bandwidth noise reaches the ADC; aliasing occurs. |
| Capacitor | Open | Vout = Vin (no shunt path) | High-frequency noise passes; DC accuracy remains intact. |
| Capacitor | Short | Vout = 0V (signal grounded) | Total signal loss; may overload the preceding driver stage. |
Design Walkthrough: Sizing an Anti-Aliasing Filter for an ESP32
Let's design a physical filter for an ESP32 reading a slow-moving analog temperature sensor (like an LM35). The ESP32 uses a Successive Approximation Register (SAR) ADC. According to Analog Devices' guidelines on ADC input filtering, SAR ADCs require a low-impedance source to charge their internal sampling capacitor (typically 10pF to 20pF) during the brief acquisition window.
Step 1: Define the Nyquist Limit and Cutoff
We are sampling at 10 kHz. The Nyquist frequency is 5 kHz. To prevent aliasing, we want our -3dB cutoff ($f_c$) to be at or below 2 kHz, giving us a comfortable guard band.
Step 2: Select the Capacitor (C)
We need a capacitor large enough to act as a charge reservoir for the ADC's internal sampling cap (rule of thumb: external C should be at least 10x to 100x the internal C). Let's pick 100 nF.
Critical Material Choice: Do not use X7R or Y5V dielectrics for precision analog filtering. They exhibit severe voltage coefficients (capacitance drops as voltage rises) and microphonics. Always specify C0G/NP0 ceramic or film capacitors for the shunt element.
Step 3: Calculate the Resistor (R)
Using the standard cutoff formula $f_c = \frac{1}{2\pi RC}$, we solve for R:
$R = \frac{1}{2 \pi \times 2000 \text{ Hz} \times 100 \times 10^{-9} \text{ F}} = 795.7 \Omega$
Step 4: Pick the Standard Value
The closest standard E12 series resistor is 820Ω.
Recalculating the actual cutoff: $f_c = \frac{1}{2 \pi \times 820 \times 100\text{nF}} = 1941 \text{ Hz}$. This is perfect.
Step 5: Verify Source Impedance
The ESP32 ADC input impedance varies, but the 820Ω series resistor is well below the typical 10 kΩ maximum source impedance recommended for 12-bit SAR ADCs. The 100nF capacitor will easily supply the instantaneous kickback current required during the sampling phase, preventing missing codes and non-linearity.
Breadboard Testing Protocol: Verifying the -3dB Cutoff
Before committing this low pass filter circuit diagram to a PCB, validate it on a breadboard. Parasitic capacitance on a breadboard (typically 2pF to 5pF between adjacent rows) won't significantly affect a 1.94 kHz filter, but it will ruin a 10 MHz RF filter. For our audio/sensor range, breadboarding is highly reliable.
- Wire the Topology: Insert the 820Ω resistor so it bridges the center divider of the breadboard. Connect your function generator's output to the resistor's input lead (Node 1). Insert the 100nF C0G capacitor between the resistor's output lead (Node 2) and the ground rail.
- Establish the Baseline: Set the function generator to output a 10 Hz sine wave at 2.0 Vpp. Connect your oscilloscope probe (set to 10x to minimize probe capacitance loading) to Node 2. Verify that the output is exactly 2.0 Vpp. At 10 Hz, the filter's attenuation is negligible.
- Calculate the -3dB Target: The -3dB point represents a voltage drop to 70.7% of the input. Calculate your target: $2.0 \text{ Vpp} \times 0.707 = 1.414 \text{ Vpp}$.
- Sweep the Frequency: Slowly increase the function generator frequency while monitoring the oscilloscope's peak-to-peak voltage. As you pass 500 Hz, 1 kHz, and 1.5 kHz, note the steady decline in amplitude.
- Pinpoint the Cutoff: Stop sweeping when the oscilloscope reads exactly 1.41 Vpp. Check the frequency counter on your function generator or scope. It should read approximately 1.94 kHz. If it reads significantly higher, your capacitor is likely out of tolerance or you accidentally grabbed an X7R cap that has lost capacitance due to DC bias.
- Verify Roll-off: Increase the frequency to 19.4 kHz (one decade above $f_c$). The amplitude should drop to roughly 0.14 Vpp (a -20dB attenuation), confirming the -20dB/decade slope.
Final Verdict: When to Upgrade to a Sallen-Key Active Filter
The 1st-order RC topology is the undisputed king of low-frequency sensor conditioning. However, fundamental filter theory dictates that a single pole can only reject so much noise. If your environment is plagued by a 50 kHz switching regulator noise and you are sampling at 100 kHz, a 1st-order RC filter will only attenuate that 50 kHz noise by about -28dB. That might still be enough to cause aliasing artifacts in a high-resolution 16-bit ADC.
The Upgrade Path: If you need > -40dB of rejection near your Nyquist limit, or if you must drive a 50Ω transmission line, abandon the passive RC design. Transition to a 2nd-order Sallen-Key unity-gain active filter.
Concrete Part Pick for Active Upgrades: For audio or precision DC up to 100 kHz, use the Texas Instruments OPA2134 or the TL072 (for budget-constrained, higher-noise-tolerance applications). Wire them in a unity-gain Sallen-Key configuration with two 10 kΩ resistors and two 1 nF C0G capacitors to achieve a sharp 15.9 kHz cutoff with a buffered, low-impedance output that will drive any ADC or cable without load-dependent shifting.
For the vast majority of DIY and commercial MCU sensor interfaces, however, the 820Ω / 100nF passive RC filter remains the most robust, cost-effective, and fail-safe choice available.
