The Problem: A Classic RC Low-Pass Example of Filter Analysis
When transitioning from textbook schematics to the workbench, the most common point of failure in basic signal conditioning is ignoring the load. Below is a standard exam-style problem that mirrors a real-world debugging scenario when smoothing PWM signals from microcontrollers like the ESP32.
A student designs a passive RC low-pass filter to smooth a 5V, 20 kHz PWM signal from an ESP32 GPIO into a steady DC voltage for an analog sensor input. They select R1 = 1 kΩ and C1 = 100 nF, calculating an unloaded cutoff frequency (fc) of 1591 Hz. However, the filter drives a 10 kΩ ADC input (RL). Calculate the actual -3dB cutoff frequency and the DC voltage gain when the load is connected.
The Trap and the Theorem: Why Unloaded Math Fails
The Trap: The initial calculation assumes the filter operates in a vacuum, using the standard formula fc = 1 / (2πR1C1). This is only true if the load impedance is infinite (an open circuit). In reality, the 10 kΩ ADC input forms a resistive voltage divider with the 1 kΩ series resistor, dropping your maximum DC voltage. Furthermore, from an AC small-signal perspective, the load resistor sits in parallel with the capacitor's reactance, altering the circuit's time constant.
The Theorem: To solve this rigorously, we apply Thevenin’s Theorem. We must find the Thevenin equivalent voltage (Vth) and Thevenin equivalent resistance (Rth) "seen" by the capacitor. The true cutoff frequency depends entirely on Rth, not just R1.
Step-by-Step Algebraic Solution
Here is the exact algebraic sequence to find the true behavior of this example of filter circuitry under load.
Step 1: Calculate the DC Gain (Thevenin Voltage)
At 0 Hz (DC), the capacitor acts as an open circuit. The circuit reduces to a simple voltage divider between R1 and RL.
- Formula: Gain (ADC) = RL / (R1 + RL)
- Substitution: ADC = 10,000 / (1,000 + 10,000)
- Calculation: ADC = 10,000 / 11,000 = 0.909 V/V (or -0.83 dB)
- Max Output Voltage: 5V × 0.909 = 4.545V
Step 2: Calculate the Thevenin Equivalent Resistance
To find the resistance "seen" by the capacitor, we short the input voltage source (the ESP32 GPIO) to ground and look back into the capacitor terminals. R1 and RL are now in parallel.
- Formula: Rth = (R1 × RL) / (R1 + RL)
- Substitution: Rth = (1,000 × 10,000) / (1,000 + 10,000)
- Calculation: Rth = 10,000,000 / 11,000 = 909.09 Ω
Step 3: Calculate the Actual Cutoff Frequency
Now we apply the standard RC cutoff formula, but substitute R1 with our newly derived Rth.
- Formula: fc(actual) = 1 / (2π × Rth × C1)
- Substitution: fc(actual) = 1 / (2 × 3.14159 × 909.09 × 100 × 10-9)
- Calculation: fc(actual) = 1 / 0.00057135 = 1750.2 Hz
Sanity Check and Independent Verification
Before trusting the math, run a rapid sanity check on the order of magnitude and logical direction:
- Direction Check: Rth (909 Ω) is less than R1 (1000 Ω). Because cutoff frequency is inversely proportional to resistance, fc must increase. Our answer (1750 Hz) is greater than the unloaded baseline (1591 Hz). The logic holds.
- Gain Check: A passive resistive network cannot amplify. Our DC gain (0.909) is strictly less than 1. The logic holds.
- Units: Ohms multiplied by Farads yields seconds (the time constant τ). The inverse of seconds is Hertz. Units are correct.
To verify this independently on the bench, do not rely on a multimeter's frequency mode. Connect a function generator set to a 1 Vpp sine wave into the filter input. Sweep the frequency from 100 Hz to 10 kHz while monitoring the output on an oscilloscope. The -3dB point will occur where the output amplitude drops to 0.707 × (1V × 0.909) = 0.642 Vpp. You will observe this crossing precisely at 1.75 kHz.
Decision Tree: Picking Your Filter Topology
Knowing how to calculate the load effect is only half the battle. The real engineering decision is choosing whether to accept that effect or eliminate it. Use this decision matrix to terminate your design phase with a concrete part selection.
| Condition / Constraint | Topology Choice | Concrete Part / Action |
|---|---|---|
| RL > 100 × R1 (e.g., driving a 10MΩ scope probe) | Passive RC (Unbuffered) | Standard 1kΩ / 100nF. Error is <1%, acceptable. |
| RL < 100 × R1 AND exact DC voltage is required | Active LPF (Buffered) | DEFAULT PICK: Texas Instruments LMV321 op-amp in unity-gain configuration. |
| High current power supply filtering (e.g., 12V motor rail) | LC Pi Filter | 10μH power inductor + 2x 22μF X7R ceramic caps. |
The Verdict: If your load impedance is unknown, varies (like plugging into different multimeters), or is below 100 kΩ, always buffer a passive RC filter with a unity-gain op-amp. The LMV321 is rail-to-rail, operates perfectly on a single 5V supply, and costs roughly $0.50 in single quantities. It presents a near-infinite input impedance to your RC network, completely eliminating the load trap calculated above.
Frequently Asked Questions
Q: Does the capacitor value affect the DC gain in this example of filter analysis?
A: No. At 0 Hz (DC), an ideal capacitor exhibits infinite reactance (an open circuit). The DC gain is determined strictly by the resistive voltage divider formed by R1 and RL. However, in the real world, if you use a cheap electrolytic capacitor with high leakage current, that leakage acts as a parallel resistance and will slightly drag down your DC voltage. Stick to C0G/NP0 or X7R ceramics for precision signal filtering.
Q: How do I simulate this exact load trap in LTspice?
A: Build the schematic with V1 (AC 1V, DC 5V), R1 (1k), C1 (100n), and RL (10k) to ground. Run an AC analysis using the command .ac dec 100 1 100k. When you probe the output node, LTspice will show the DC baseline at 0.909V. To find the -3dB point, use the cursor to find where the trace drops to 0.642V. For a more automated approach, utilize the Analog Devices Filter Wizard to generate active topologies that inherently solve this loading issue.
Q: What happens to the PWM ripple if the microcontroller frequency drops?
A: The filter's attenuation at the fundamental frequency dictates your ripple. With a true fc of 1750 Hz, a 20 kHz PWM signal is attenuated by roughly -21dB (excellent smoothing). But if your ESP32 code drops the PWM frequency to 1 kHz to increase resolution, the signal is now below the cutoff frequency. The filter will pass the 1 kHz square wave almost entirely, resulting in massive voltage ripple at your ADC. Always verify your software PWM settings against your hardware's actual loaded cutoff frequency.
