Schematic Symbols and Topology Reference
When reading a datasheet or reverse-engineering a PCB, you will encounter two primary schematic standards. The symbol itself doesn't change, but its topological placement defines its function. Use this table to identify what you are looking at on the schematic sheet.
| Standard / Topology | Visual Symbol | Schematic Orientation | Practical Meaning on the Bench |
|---|---|---|---|
| IEEE 315 (US Standard) | Zigzag line (4 peaks) | Vertical, top node to VCC | Standard pull-up in North American schematics. Top node connects to 3.3V or 5V rail. |
| IEC 60617 (Global Standard) | Hollow rectangle | Vertical, top node to VCC | Standard pull-up in European/Asian schematics. Often annotated with 'R_pu' or 'R_pullup'. |
| Pull-Down Topology | Zigzag or Rectangle | Vertical, bottom node to GND | Biases the line LOW. Used on MOSFET gates to prevent false turn-on during MCU boot. |
| Series / Current Limiting | Zigzag or Rectangle | Horizontal, inline with signal | NOT a pull-up. Limits current into an LED or terminates a high-speed transmission line. |
| Open-Drain Bus (I2C) | Zigzag or Rectangle | Vertical to VCC, shared node | Multiple devices share the pulled-up line. The resistor provides the HIGH state for the whole bus. |
Pull-Up Resistor Value Selection Matrix
Selecting the correct resistance value is where most hobbyists and junior engineers fail. A pull-up resistor forms an RC low-pass filter with the parasitic capacitance of the PCB traces and input pins. If the resistance is too high, the voltage rise time ($t_r$) will be too slow, causing data corruption on high-speed buses like I2C. If it is too low, it will waste power and may exceed the sink current limit of the open-drain driver.
According to the NXP I2C-bus specification (UM10204), the maximum bus capacitance is 400 pF, and the rise time must not exceed 300 ns for Fast-mode (400 kHz) operation. The Texas Instruments SLVA689 pull-up calculation guide provides the exact formulas for calculating minimum and maximum bounds based on $V_{OL}$ (output low voltage) and bus capacitance.
| Resistance Value | Primary Use Case | Rise Time Impact (at 200pF load) | Current Draw (when pulled LOW) | Sink Capability Required |
|---|---|---|---|---|
| 1.0 kΩ | I2C High-Speed (1 MHz+), short heavy buses | ~170 ns (Very Fast) | 3.3 mA | Must sink ≥ 3.3 mA (check MCU datasheet) |
| 2.2 kΩ | I2C Fast-mode (400 kHz), standard sensor modules | ~374 ns (Fast) | 1.5 mA | Must sink ≥ 1.5 mA |
| 4.7 kΩ | I2C Standard-mode (100 kHz), general GPIO inputs | ~798 ns (Moderate) | 0.7 mA | Must sink ≥ 0.7 mA |
| 10 kΩ | Push-button switches, low-speed MCU GPIO, reset lines | ~1.7 µs (Slow, fine for human input) | 0.33 mA | Must sink ≥ 0.33 mA |
| 100 kΩ | Ultra-low power battery nodes, CMOS chip enables | ~17 µs (Very Slow, unusable for I2C) | 0.033 mA (33 µA) | Must sink ≥ 33 µA |
If you are designing or repairing switch-mode power supplies (SMPS) or tube amplifiers, pull-up resistors on the primary side may be tied to 170V DC or higher bus rails. These resistors must be rated for the appropriate voltage (often requiring two or three series 1206 resistors to prevent internal arcing) and power dissipation. De-energize the circuit, wait for bulk capacitors to bleed down, and verify dead with a CAT III/IV meter before probing.
Rows People Get Wrong and Faded Board Diagnostics
When interpreting the tables and schematics above, a few specific rows and real-world scenarios consistently cause debugging headaches.
Rows People Get Wrong
- Confusing the IEC Rectangle (Table 1): Beginners frequently mistake the IEC hollow rectangle for a relay coil, a fuse, or a capacitor plate, especially if the 'R' designator (e.g., R14) is obscured. Always trace the nodes: if one side hits a logic rail and the other hits a gate/base/input, it is a resistor.
- Using 10 kΩ for I2C Fast-Mode (Table 2): Many breakout boards ship with 10 kΩ pull-ups. While this works for 100 kHz Standard-mode, attempting to run a 400 kHz I2C bus with 10 kΩ resistors will result in trapezoidal waveforms that fail to cross the logic HIGH threshold in time, throwing 'NACK' or 'Bus Error' faults on your ESP32 or Raspberry Pi.
- Parallel Pull-Up Stacking: If you plug in three I2C sensors, each with its own 4.7 kΩ pull-up resistors on the SDA/SCL lines, they are in parallel. The effective pull-up becomes ~1.56 kΩ. This lowers the rise time but forces the open-drain MOSFETs to sink over 2 mA per line, which can exceed the absolute maximum ratings of smaller sensor ICs.
Safe Interpretation When Markings are Faded or Missing
On older PCBs, rework boards, or cheap clones, the silkscreen designator ('R12') or the value ('472' for 4.7k) may be scraped off, burned away, or covered in conformal coating. Here is how to safely identify a pull-up resistor without relying on visual markings:
- Power Down and Isolate: Remove all power sources, including backup coin cells, to prevent false continuity readings and protect your meter.
- Trace the VCC Node: Set your multimeter to continuity mode. Place one probe on a known VCC test point (or the VCC pin of the adjacent microcontroller). Probe the pads of the unmarked component. If one pad beeps continuously to VCC, it is a strong candidate for a pull-up.
- Trace the Signal Node: Move the VCC probe to the GPIO, Reset, or I2C pin of the MCU. If the other pad of the component beeps to the MCU pin, you have confirmed a pull-up topology.
- Measure the Value: Once identified, switch your meter to the Ohms (Ω) setting. Measure across the component pads. Note: If the component is still soldered to the board, the MCU's internal protection diodes or parallel bus traces may give you a falsely low reading. For an exact value, desolder one leg of the resistor and lift it off the pad before measuring.
Regional Standards: IEEE 315 vs. IEC 60617
The visual representation of the pull-up resistor depends entirely on the regional standard adopted by the drafting engineer or the EDA software's default library.
- IEEE 315 (North America): Uses the zigzag symbol. This is the default in most US-based universities and legacy schematics. If you are using KiCad or Altium in the US, your default library will likely pull the zigzag symbol. It is highly recognizable but can look cluttered in dense BGA fanout schematics.
- IEC 60617 (Europe, UK, Asia, Australia): Uses the rectangular box symbol. This is the mandated standard for most modern international manufacturing and is the default in many European engineering firms. It scales much better on complex, multi-page schematics because the clean lines don't visually bleed into adjacent routing.
Regardless of the symbol shape, the electrical rule remains identical: the component must be placed between the signal node and the positive supply rail. Always verify the schematic's title block to confirm which standard the drafting engineer used, as this dictates how you interpret other passive components (like inductors and capacitors) on the same page.
