What Defines a Precision Op Amp (And What Doesn't)
A standard operational amplifier like the LM358 might have an input offset voltage (V_os) of 3 mV to 7 mV. A precision op amp is strictly defined by a V_os of less than 100 µV, low offset drift over temperature (typically < 1 µV/°C), and high open-loop gain (> 120 dB). If you are amplifying a 10 mV signal from a load cell or a thermocouple, a 3 mV offset introduces a 30% error before you even write a line of firmware. Precision op amps eliminate this static error.
The industry-standard pinout for a dual precision op amp in an 8-pin DIP or SOIC package is universal. When reading the datasheet or looking at the silkscreen, the pin mapping is:
- Pin 1: Output A
- Pin 2: Inverting Input A (In-)
- Pin 3: Non-Inverting Input A (In+)
- Pin 4: V- (Negative Supply or Ground)
- Pin 5: Non-Inverting Input B (In+)
- Pin 6: Inverting Input B (In-)
- Pin 7: Output B
- Pin 8: V+ (Positive Supply)
Operation Regions and Biasing Rules
To use a precision op amp correctly, you must keep it in its linear region and respect its Input Common-Mode Voltage Range (ICMR). Pushing the inputs outside the ICMR causes phase reversal or latch-up, where the output pegs to the opposite rail and stays there until power is cycled.
| Region | Input Condition | Typical Output Voltage | Typical Output Current |
|---|---|---|---|
| Linear (Active) | V+ ≈ V- (within µV), inside ICMR | 0.1V to 4.9V (V_supply - V_sat) | < 30 mA (within SOA) |
| Positive Saturation | V+ > V- by > 1 mV | Clamped at ~4.95V (V_cc - 50mV) | Limited by R_load or I_sc (~40mA) |
| Negative Saturation | V- > V+ by > 1 mV | Clamped at ~0.05V (V_ee + 50mV) | Limited by R_load or I_sc (~40mA) |
| Latch-up / Fault | Inputs exceed ICMR or V_supply | Unpredictable (often pegged high) | Can exceed 50mA (thermal risk) |
How to Bias for the Job
Dual Supply (+/- 5V or +/- 15V): Biasing is trivial. Tie V- to the negative rail, V+ to the positive rail, and reference your input signals to actual ground (0V). The ICMR almost always includes 0V.
Single Supply (e.g., 5V or 3.3V): You must create a virtual ground. Use a precision voltage divider (two 10kΩ 0.1% resistors) buffered by another op amp to create a 2.5V V_ref. Tie your non-inverting input to V_ref. This centers your AC signal in the linear region and prevents the negative half-wave from clipping at 0V.
The Decision Tree: Picking Your Default Part
Stop scrolling through parametric tables. Use this decision path to select the exact part number for your sensor front-end.
| If your application requires... | Then select this architecture... | Concrete Part Number (Dual) |
|---|---|---|
| Ultra-low DC offset (< 5 µV) for thermocouples or RTDs | Zero-Drift / Chopper-Stabilized CMOS | ADA4522-2 (Analog Devices) |
| Ultra-low voltage noise (< 2 nV/√Hz) for audio or piezo sensors | Bipolar Low-Noise | OPA211 (Texas Instruments) |
| Micropower battery operation (< 50 µA) with decent precision | Zero-Drift CMOS, Low Quiescent Current | OPA2188 (Texas Instruments) |
| High voltage industrial sensing (> 36V rails) | High-Voltage Precision Bipolar | OPA2277 (Texas Instruments) |
Application Circuit: 100Hz Active Low-Pass Sensor Amplifier
Below is a complete, buildable non-inverting amplifier with a first-order RC low-pass filter, optimized for conditioning a 10 mV DC sensor signal with high-frequency EMI rejection. We are using the OPA211 on a +/- 5V dual supply.
Component Values and Wiring
- U1: OPA211 (Pins 4 to -5V, Pin 8 to +5V)
- R_g (Gain set to ground): 10 kΩ (0.1% metal film)
- R_f (Feedback from Out to In-): 90 kΩ (0.1% metal film) Yields a non-inverting gain of 1 + (90k/10k) = 10 V/V.
- R_filt (Series resistor before filter cap): 16 kΩ (1%)
- C_filt (Capacitor from filter node to ground): 100 nF (C0G/NP0 dielectric)
How the Circuit Works
- Amplification: The sensor signal enters Pin 3 (In+). The feedback loop forces Pin 2 (In-) to match Pin 3. The output (Pin 1) drives 10x the input voltage.
- Filtering: The amplified signal passes through R_filt (16 kΩ) and is shunted to ground by C_filt (100 nF). The cutoff frequency is calculated as f_c = 1 / (2 * π * R * C). Using our values: 1 / (2 * 3.14159 * 16000 * 0.0000001) = 99.47 Hz.
- Output: Take your final signal from the junction of R_filt and C_filt. The C0G dielectric on the capacitor is critical; X7R capacitors exhibit piezoelectric effects and voltage coefficient errors that will ruin your precision DC measurement.
Failure Modes and Bench Testing with a DMM
Precision op amps rarely fail from old age; they fail from Electrical Overstress (EOS), Electrostatic Discharge (ESD), or latch-up events. When a circuit fails on the bench, use a digital multimeter (DMM) like a Fluke 87V to isolate the fault.
Top 3 Failure Modes
- Input Stage ESD Blowout: A static zap destroys the input differential pair. Symptom: Massive offset voltage, or inputs draw mA-level bias currents instead of nA/pA.
- Output Stage Short: Driving a capacitive load > 100 nF without a series isolation resistor causes high-frequency oscillation, overheating the output transistors until they short to the supply rail.
- Latch-up: Exceeding the ICMR injects current into the substrate, triggering a parasitic SCR. The chip draws massive quiescent current and gets hot to the touch.
Step-by-Step DMM Diagnostic Procedure
Step 1: The Power Rail Short Check (Power OFF)
Set your DMM to continuity or resistance mode. Measure between Pin 8 (V+) and Pin 4 (V-). You should read > 10 kΩ. If you read < 50 Ω, the internal power bus is shorted. Desolder and replace.
Step 2: Input Protection Diode Check (Power OFF)
Set DMM to Diode Test mode. Place the red probe on Pin 3 (In+) and black probe on Pin 8 (V+). You should read ~0.6V for bipolar inputs (OPA211) or "OL" (Open Loop) for CMOS inputs (ADA4522). Reverse the probes (red on V+, black on In+); it should read OL. If you read 0.00V in either direction, the ESD clamp diode is shorted.
Step 3: The Virtual Ground Output Test (Power ON)
Power the circuit. Tie Pin 2 (In-) and Pin 3 (In+) directly to your circuit ground (or V_ref for single supply). Measure Pin 1 (Output) with the DMM in DC Volts.
Expected Result: The output should read 0.000V (or V_ref) +/- the part's V_os. For an OPA211, expect < 50 µV. For an ADA4522, expect < 10 µV.
Failure Symptom: If the output is pegged at +4.9V or -4.9V, the op amp is either latched, the feedback loop is broken (check R_f for an open solder joint), or the input stage is destroyed.
