When power electronics engineers ask what is positive temperature coefficient (PTC) behavior, they are referring to a fundamental material property where electrical resistance increases as temperature rises. In circuit design, PTC is a double-edged sword. On one hand, specialized PTC thermistors act as self-resetting fuses for overcurrent protection. On the other hand, the inherent PTC effect in silicon power MOSFETs and copper PCB traces means that as your components get hotter, their resistive losses ($I^2R$) increase, generating even more heat.
Managing this thermal feedback loop requires moving beyond simple wattage ratings and diving into junction-to-ambient thermal resistance ($R_{\theta JA}$) math. This guide breaks down how PTC impacts thermal limits, how to interpret derating curves, and how to select the right heatsink based on real-world airflow dynamics.
The PTC Effect: How Hot Is Too Hot?
To manage heat, you first need to know the absolute thermal limits of the materials in your power path. The PTC effect dictates that a copper trace carrying 20A will have a higher DC resistance at 80°C than it does at 25°C. For silicon MOSFETs, the on-state resistance ($R_{DS(on)}$) typically exhibits a strong PTC, often doubling by the time the junction reaches 125°C. While this PTC behavior is actually beneficial for paralleling MOSFETs (the hotter device takes less current, preventing DC current hogging), it severely impacts your total conduction losses.
So, how hot is too hot? The answer depends on the specific material layer in your thermal stack. Pushing components to their absolute datasheet maximums guarantees premature failure. Below is a data-dense breakdown of PTC behaviors and practical thermal limits for common power electronics materials.
| Material / Component | PTC Behavior Profile | Max Absolute Temp | Practical Design Limit | Failure Signature of Thermal Stress |
|---|---|---|---|---|
| Silicon (MOSFET Junction) | Linear +0.5% to +1.0% / °C | 150°C - 175°C | 110°C - 125°C | Gate oxide puncture, bond wire lift-off, parametric drift |
| Copper (PCB Traces) | Linear +0.39% / °C | 105°C (Standard FR4) | 85°C - 95°C | FR4 delamination, trace lifting, solder joint creep |
| Barium Titanate (PTC Thermistor) | Exponential spike at Curie point | 125°C (Typical Trip) | N/A (Designed to trip) | Ceramic cracking, loss of trip hysteresis, contact degradation |
| Aluminum (Heatsink Alloy 6063) | Linear +0.2% / °C (Resistivity) | 660°C (Melting) | 100°C (Surface safety) | Structural warping (rare), TIM pump-out due to CTE mismatch |
Notice the gap between the "Max Absolute Temp" and the "Practical Design Limit." Running a silicon junction at 170°C might not instantly destroy the die, but the thermal expansion mismatch between the silicon, the copper leadframe, and the epoxy package will cause mechanical fatigue. The most common failure signature of chronic thermal stress in TO-220 and D2PAK packages is solder joint creep and bond wire lift-off, leading to an open-circuit failure.
Thermal Path Math and Derating Curves
You cannot select a heatsink based on a component's headline wattage rating. A MOSFET datasheet might claim a power dissipation ($P_D$) of 200W, but that figure is only valid if the case temperature ($T_C$) is held at exactly 25°C—an impossibility in real-world applications without liquid nitrogen.
To find your actual thermal budget, you must interpret the datasheet's derating curve. The curve shows a linear drop from the maximum power at 25°C down to 0W at the maximum junction temperature ($T_J$). For a 200W part with a 175°C max $T_J$, the derating factor is $200W / (175°C - 25°C) = 1.33W/°C$. If your thermal design results in a case temperature of 100°C, your allowable power drops to $200W - (1.33 \times 75) = 100W$.
To calculate the required heatsink performance, we use the thermal equivalent of Ohm's Law, where temperature is voltage, power is current, and thermal resistance ($R_{\theta}$) is electrical resistance:
$T_J = T_A + P_D \times (R_{\theta JC} + R_{\theta CS} + R_{\theta SA})$
Where:
$T_J$ = Junction Temperature (°C)
$T_A$ = Ambient Temperature (°C)
$P_D$ = Power Dissipation (W)
$R_{\theta JC}$ = Junction-to-Case thermal resistance
$R_{\theta CS}$ = Case-to-Sink thermal resistance (TIM)
$R_{\theta SA}$ = Sink-to-Ambient thermal resistance
Worked Example: Let's design a thermal path for an Infineon IRFB4110PbF MOSFET switching a 30W continuous load inside an enclosed motor controller.
- Target $T_J$: 125°C (keeping it well below the 175°C absolute max for reliability).
- $T_A$: 45°C (ambient inside the enclosure under load).
- $P_D$: 30W (accounting for the PTC increase in $R_{DS(on)}$ at elevated temps).
- $R_{\theta JC}$: 0.45 °C/W (from datasheet).
- $R_{\theta CS}$: 0.20 °C/W (using a high-quality Bergquist Sil-Pad 900VOS thermal interface material).
First, find the total allowable thermal resistance ($R_{\theta JA}$):
$R_{\theta JA} = (T_J - T_A) / P_D = (125 - 45) / 30 = 2.66 °C/W$.
Next, isolate the heatsink requirement ($R_{\theta SA}$):
$R_{\theta SA} = R_{\theta JA} - R_{\theta JC} - R_{\theta CS} = 2.66 - 0.45 - 0.20 = 2.01 °C/W}$.
You need a heatsink with a sink-to-ambient thermal resistance of 2.01 °C/W or lower. If you rely solely on passive convection, you will need a massive, heavy extruded aluminum profile. This is where enclosure and airflow modifications become critical.
Heatsink Selection: What Airflow and Enclosure Changes Buy You
Passive heatsinks rely on natural convection and radiation, which are highly inefficient for compact power electronics. A standard TO-220 stamped heatsink like the Aavid Thermalloy 530002B02500G has a passive $R_{\theta SA}$ of roughly 18 °C/W—useless for our 2.01 °C/W target. Even a larger extruded profile like the CUI Devices HSE-402-04HA (40mm x 40mm x 20mm) sits at about 5.5 °C/W in still air.
To bridge this gap, you have two levers: change the enclosure environment, or introduce forced airflow.
1. What Airflow Changes Buy You
Adding forced convection drastically alters the boundary layer of stagnant air clinging to the heatsink fins. If we mount a 40mm exhaust fan (like a Noctua NF-A4x20 PWM) directly over the CUI Devices HSE-402-04HA, pushing air at just 1.0 meters per second (m/s), the thermal resistance plummets from 5.5 °C/W down to approximately 1.8 °C/W. This single airflow change pushes the design safely under our 2.01 °C/W requirement, saving you the cost and weight of a much larger passive heatsink.
2. What Enclosure Changes Buy You
Often, the limiting factor isn't the heatsink; it's the localized ambient temperature ($T_A$) inside a sealed enclosure. If your enclosure traps heat from adjacent magnetics or gate drivers, $T_A$ can easily spike from a room-temperature 25°C to a localized 55°C.
Because of the PTC effect, as the MOSFET heats up, its $R_{DS(on)}$ increases, causing it to dissipate more wattage for the same load current. If your enclosure lacks adequate exhaust ventilation, this increased wattage raises the internal $T_A$, which further reduces the heatsink's ability to shed heat. This positive feedback loop is a primary cause of thermal runaway in poorly ventilated motor drives. Always calculate $T_A$ based on the internal enclosure temperature at steady state, not the room temperature.
By adding a simple 80mm chassis exhaust fan to the enclosure, you flush the trapped hot air, dropping the localized $T_A$ from 55°C back down to 35°C. Looking back at our math, dropping $T_A$ by 20°C increases your allowable $R_{\theta JA}$ from 2.66 °C/W to 3.33 °C/W. This gives you a much wider margin for error and allows you to use a cheaper, smaller heatsink.
Ultimately, understanding what is positive temperature coefficient behavior forces you to design for the worst-case hot state, not the 25°C benchtop ideal. By combining accurate $R_{\theta}$ math, realistic derating interpretations, and targeted airflow, you can keep your PTC silicon well within its safe operating area.
For further reading on thermal interface materials and heatsink sizing, refer to the CUI Devices Thermal Resistance Guide and All About Circuits' breakdown of PTC thermistors.
