The Four Topologies of Reverse Polarity Protection
Hooking up a 12V battery backward to a custom PCB is a rite of passage, but it shouldn't mean your $40 microcontroller goes up in smoke. A reverse polarity protection circuit sits between your power source and your load, acting as a one-way valve. While there are several ways to skin this cat, the P-Channel MOSFET (PMOS) topology is the undisputed king for 90% of maker and industrial DC applications.
Before we wire up the PMOS, let's look at why we reject the alternatives for medium-power designs. Here is how the four standard topologies stack up:
| Topology | Voltage Drop | Power Loss (at 5A) | Component Cost | Verdict |
|---|---|---|---|---|
| Series Schottky Diode | ~0.4V | 2.0W | $0.10 | Fine for <1A. At 5A, it needs a massive heatsink. |
| Shunt Diode + Fuse | 0V (until fault) | 0W (until fault) | $0.20 | Destructive. Blows the fuse and requires user intervention. |
| High-Side PMOS | ~0.07V | 0.35W | $0.45 | The Sweet Spot. Low loss, auto-resetting, no heatsink. |
| Ideal Diode IC (e.g., LT4357) | ~0.02V | 0.15W | $3.50+ | Overkill for <10A. Use for 48V telecom or high-current automotive. |
The Decision Path: Which Topology Do You Actually Need?
Stop guessing and follow this decision tree to pick your protection scheme:
- IF Load Current < 0.5A AND Voltage Drop doesn't matter → Use a Series 1N5819 Schottky Diode.
- IF Load Current is 1A to 10A AND Vin < 30V → Use a High-Side PMOS (Default Pick).
- IF Load Current > 10A OR Vin > 30V OR you need OR-ing redundancy → Use an Ideal Diode Controller like the Analog Devices LT4357.
PMOS Topology Deep Dive: Node Labels and Behavior
The most common mistake hobbyists make with a PMOS protector is orienting the MOSFET backward. Unlike an N-Channel low-side switch, a high-side PMOS protector relies on its internal body diode to bootstrap the gate voltage.
Here are the exact node labels for the high-side PMOS topology:
- Drain (D): Connects to VIN (the raw, unprotected power input).
- Source (S): Connects to VOUT (the protected output feeding your load).
- Gate (G): Pulled to GND via a resistor (R1), and clamped to Source via a Zener diode (D1).
When VIN goes positive, current flows through the PMOS body diode (which points from Drain to Source) to VOUT. This raises the Source voltage to VIN - 0.7V. Because the Gate is tied to GND (0V), the Gate-to-Source voltage (Vgs) becomes roughly -11.3V on a 12V system. This negative Vgs turns the PMOS channel ON hard, bypassing the body diode and dropping the voltage loss to mere millivolts.
Behavior Table: What Changes When Elements Shift
| Condition / Fault | Vgs (Gate-to-Source) | PMOS State | Result at Load (VOUT) |
|---|---|---|---|
| Normal Operation (VIN = +12V) | ~-12V (Clamped by Zener) | Fully ON (Rds(on)) | ~11.95V (Minimal drop) |
| Reverse Polarity (VIN = -12V) | 0V | OFF | 0V (Protected) |
| R1 (Gate Pull-down) Opens | Floating / Undefined | Unpredictable | PMOS may operate in linear region and overheat. |
| Zener Diode Shorts | 0V | OFF | 0V (Circuit fails safe, but load loses power). |
Design Walkthrough: Sizing a 12V / 5A PMOS Protector
Let's build a concrete circuit for a 12V nominal system (up to 15V transient) drawing a continuous 5A. We need real component values, not just schematic symbols.
1. Selecting the PMOS (The Pass Element)
We need a P-Channel MOSFET with a Vds(max) safely above our 15V transient, and an Rds(on) low enough to avoid needing a heatsink.
The Pick: FDS4435B (SO-8 package).
- Vds(max): -30V (Safe margin for 12V nominal / 15V spikes).
- Id(max): -10A (Plenty of headroom for our 5A load).
- Rds(on): 14mΩ at Vgs = -10V.
Thermal Math: At 5A, power dissipation is I² × R = 25 × 0.014 = 0.35W. The SO-8 package has a junction-to-ambient thermal resistance of ~50°C/W. A 0.35W dissipation yields a 17.5°C temperature rise above ambient. It will run slightly warm to the touch, but requires no heatsink.
2. Sizing the Gate Network (R1 and D1)
The Gate needs to be pulled to GND to turn the MOSFET on, but we must protect the Gate oxide from overvoltage. The FDS4435B has a Vgs(max) rating of ±20V. If our 12V battery gets hit by a 24V load-dump, a direct GND tie would destroy the gate.
- R1 (Gate Pull-down): 10kΩ (0805 SMD or 1/4W through-hole). This limits current and pulls the gate to 0V when VIN is present.
- D1 (Gate Clamp): BZX84C15 (15V Zener diode, SOT-23). Place it between Gate (Cathode) and Source (Anode). If VIN spikes to 24V, the Zener clamps Vgs to -15V, saving the MOSFET. The 10k resistor limits the Zener current to less than 1mA during this fault.
Failure Modes: What Breaks at the Extremes?
A robust design anticipates how it will fail. According to Texas Instruments' Power House guidelines on protection circuits, understanding single-point failures is critical for automotive and industrial reliability. Here is what happens when components fail:
- The MOSFET Shorts (Drain-to-Source): This is the catastrophic failure mode. If the PMOS exceeds its SOA (Safe Operating Area) and shorts, your load is now directly connected to VIN with zero protection. If VIN is reversed, the body diode will conduct backward, likely destroying the load. Mitigation: Ensure Vds(max) has a 50% margin over maximum expected transients.
- The Zener Diode Opens: The circuit still works perfectly under normal 12V conditions. However, if a 24V transient hits, Vgs will exceed -20V, puncturing the gate oxide and permanently shorting the MOSFET.
- The Load Shorts to GND: If VOUT is shorted to GND while VIN is applied, the PMOS will attempt to pass infinite current. The PMOS will enter its linear region, heat up rapidly, and fail unless you have an upstream fuse or the MOSFET's internal thermal shutdown (if equipped) kicks in. Always pair this circuit with a correctly sized upstream fuse.
Step-by-Step Breadboard Testing Protocol
Do not just wire this up and plug in a 10A battery. Follow this bench protocol to verify the reverse polarity protection circuit behavior safely.
- Prep the Bench Supply: Set your lab power supply to 12.0V. Critical: Set the current limit (OCP) to 100mA. This prevents magic smoke if you wired the Gate network backward.
- Wire the Pass Element: Insert the FDS4435B. Connect Drain to the supply's positive terminal. Connect Source to your load (use a 100Ω power resistor as a dummy load for now).
- Wire the Gate Network: Connect the 10kΩ resistor from Gate to Supply GND. Connect the 15V Zener Cathode to Gate, and Anode to Source.
- Test Normal Polarity: Turn on the supply. Measure VOUT with your multimeter. It should read ~11.9V. Measure the voltage across the 10k resistor; it should read ~12V, confirming the gate is being pulled low.
- Test Reverse Polarity: Turn off the supply. Swap the supply leads (Positive to GND, Negative to VIN). Turn the supply back on. Measure VOUT. It must read 0.00V. If it reads anything above 0.5V, your MOSFET is oriented backward or the Zener is shorted.
- Verify Leakage: In the reverse state, measure the current on your bench supply. It should read less than 1mA (just the leakage of the reverse-biased body diode and Zener).
The Final Verdict: Your Default Component Pick
When designing a custom PCB or wiring a robust 12V/24V maker project, stop defaulting to bulky series diodes or destructive fuse-and-shunt setups. The high-side PMOS topology offers the best balance of low voltage drop, auto-resetting fault recovery, and low BOM cost.
The Default Recommendation: For any DC load between 1A and 8A, operating between 5V and 20V, use the FDS4435B P-Channel MOSFET, paired with a 10kΩ pull-down resistor and a BZX84C15 (15V) Zener diode.
Keep the PCB traces between the Drain/Source and your main power planes wide (minimum 40 mils for 5A with 1oz copper) to act as a passive heatsink. If your application exceeds 10A, steps up to 48V, or requires hot-swapping with massive capacitive loads, abandon the discrete PMOS and move to an Ideal Diode Controller IC to manage the gate charge and inrush current safely.






