A parallel tuned circuit consists of an inductor (L) and a capacitor (C) wired in parallel across two nodes. At its resonant frequency ($f_r = \frac{1}{2\pi\sqrt{LC}}$), the reactive currents cancel internally, presenting a theoretically infinite impedance to the external source. Unlike a series resonant circuit that passes the resonant frequency (band-pass), a parallel tuned circuit rejects it (band-stop) or stores energy as a tank. This topology is the backbone of RF oscillators, intermediate frequency (IF) filters, and impedance matching networks. Below, we break down the exact node topology, real-world component selection, and the failure modes that destroy resonance on the bench.
The Core Topology: Nodes, Components, and Resonance
The physical layout of a parallel tuned circuit is deceptively simple but demands strict attention to node definitions. The circuit operates between Node A (the top junction) and Node B (the bottom junction or ground reference). The inductor and capacitor are both connected directly between Node A and Node B.
When an AC signal is applied across these nodes, the capacitor draws a leading current while the inductor draws a lagging current. At the exact resonant frequency, these two currents are equal in magnitude but 180 degrees out of phase. They cancel each other out from the perspective of the external source, resulting in a massive spike in impedance. Internally, however, a large circulating current bounces back and forth between the magnetic field of the inductor and the electric field of the capacitor. This is why it is frequently called a "tank" circuit.
You choose a series LC topology when you need a band-pass filter, as its impedance drops to near-zero at resonance, allowing the target frequency to pass through to the load. You choose a parallel tuned circuit when you need a band-stop (notch) filter, an oscillator tank, or an impedance matching network. In a parallel configuration, the high impedance at resonance blocks the signal from reaching ground, forcing it to develop a high voltage across the nodes or routing it to an alternative path.
Design Walkthrough: Building a 10.7 MHz IF Tank
Let us design a parallel tank circuit for a standard 10.7 MHz FM radio Intermediate Frequency (IF) stage. We need to select real, off-the-shelf components rather than theoretical ideals.
- Define the Target: $f_r = 10.7 \text{ MHz}$.
- Select the Inductor: High-frequency designs usually start by fixing the inductor value based on available Q-factor and physical size. We will select a standard 2.2 µH radial leaded inductor (e.g., Bourns 78FR22K-RC).
- Calculate the Capacitor: Using the rearranged resonance formula $C = \frac{1}{(2\pi f_r)^2 L}$:
$C = \frac{1}{(2\pi \times 10.7 \times 10^6)^2 \times 2.2 \times 10^{-6}} \approx 100.56 \text{ pF}$. - Select the Capacitor: We will use a standard 100 pF C0G/NP0 ceramic capacitor (e.g., Vishay K101J15C0GF5UH5). NP0 dielectrics are mandatory here; X7R or Y5V ceramics will drift wildly with temperature and applied voltage, destroying your tuning.
The Parasitic Reality Check: Real inductors have internal series resistance ($R_s$). The Bourns 2.2 µH part has an $R_s$ of roughly 0.5 Ω. This resistance limits the peak impedance ($R_p$) of our parallel tank at resonance. The equivalent parallel resistance is calculated as $R_p \approx \frac{L}{C \times R_s}$. Plugging in our values: $R_p \approx \frac{2.2\mu}{100p \times 0.5} = 44 \text{ k}\Omega$. Therefore, at exactly 10.7 MHz, the circuit will not present infinite impedance, but rather a very real 44 kΩ peak. This dictates the load impedance your following amplifier stage must present to avoid dragging down the tank's Q-factor.
Behavioral Matrix: Tuning the Elements
When debugging or intentionally detuning a parallel LC network on the bench, you must know how altering a single variable shifts the overall response. The table below assumes a standard parallel RLC model where R represents the equivalent parallel load or parasitic loss.
| Parameter Changed | Effect on Resonant Freq ($f_r$) | Effect on Peak Impedance ($Z_{max}$) | Effect on Bandwidth (BW) |
|---|---|---|---|
| Increase Inductance (L) | Decreases | Increases (if $R_s$ is constant) | Narrows |
| Increase Capacitance (C) | Decreases | Decreases | Widens |
| Increase Parasitic $R_s$ (Inductor) | No direct change | Decreases significantly | Widens (Lower Q) |
| Add Parallel Load Resistor | No direct change | Decreases (clamped by load) | Widens (Lower Q) |
Failure Modes: What Breaks at the Extremes
On the jobsite or in the repair lab, components fail open or short. Understanding the extreme failure modes of a parallel tuned circuit saves hours of oscilloscope troubleshooting. Here is the exact failure-mode contrast between parallel and series topologies when a component dies.
- Shorted Inductor: Creates a direct DC short across Node A and Node B. The resonant frequency is destroyed. The impedance drops to near 0 Ω across all frequencies. In a series circuit, a shorted inductor simply removes the inductance, turning the circuit into a capacitive high-pass filter; in parallel, it kills the entire signal path.
- Open Inductor: The circuit degrades into a simple shunt capacitor. Resonance is lost. Impedance will steadily decrease as frequency increases ($X_c = \frac{1}{2\pi fC}$). The circuit will no longer block the target $f_r$.
- Shorted Capacitor: Identical to a shorted inductor. Node A is shorted to Node B. The tank is dead, and the signal is grounded.
- Open Capacitor: The circuit degrades into a simple shunt inductor. Resonance is lost. Impedance will steadily increase with frequency ($X_L = 2\pi fL$). The high-frequency rejection characteristic of the tank is entirely compromised.
Breadboard Testing Protocol
Testing a parallel tuned circuit requires measuring voltage amplitude across the tank while sweeping the input frequency. Follow this exact step-by-step procedure to verify your 10.7 MHz design on a solderless breadboard.
- Insert Components: Plug the 2.2 µH inductor and 100 pF capacitor into the breadboard so that both of their leads share the same respective power and ground rails (Node A and Node B).
- Add the Feed Resistor: Insert a 1 kΩ series resistor between your function generator's output cable and Node A. This resistor acts as a crude current source and creates a voltage divider with the tank's impedance.
- Probe the Circuit: Connect Channel 1 (CH1) of your oscilloscope to the function generator output (before the 1 kΩ resistor) to serve as your trigger and reference. Connect Channel 2 (CH2) directly to Node A to measure the voltage across the tank.
- Sweep the Generator: Set the function generator to output a 1 Vpp sine wave. Sweep the frequency logarithmically from 1 MHz up to 20 MHz.
- Observe the Peak: Watch CH2. At low and high frequencies, the tank's impedance is low, so most of the generator's voltage drops across the 1 kΩ feed resistor, leaving a small signal on CH2. As you approach 10.7 MHz, the tank's impedance will spike toward 44 kΩ. The voltage on CH2 will peak sharply, approaching the 1 Vpp of CH1.
A standard solderless breadboard introduces roughly 2 pF to 5 pF of stray capacitance between adjacent contact strips. In a 100 pF tank, this will shift your resonant frequency down by about 1% to 2.5%. If your scope shows a peak at 10.5 MHz instead of 10.7 MHz, do not immediately blame the components—account for the breadboard's parasitic capacitance or move the validation to a soldered protoboard.
Frequently Asked Questions
How does a parallel tuned circuit differ from a series resonant circuit?
The fundamental difference lies in impedance behavior and current magnification. A series resonant circuit exhibits minimum impedance at resonance, acting as a band-pass filter, and the voltage across the individual L and C components can be magnified to many times the source voltage (voltage magnification). A parallel tuned circuit exhibits maximum impedance at resonance, acting as a band-stop filter or tank, and the internal circulating current between the L and C can be many times greater than the current drawn from the external source (current magnification).
Why does a parallel LC circuit have maximum impedance at resonance?
At resonance, the inductive reactance ($X_L$) and capacitive reactance ($X_C$) are exactly equal in magnitude. Because the current through an inductor lags the voltage by 90 degrees, and the current through a capacitor leads the voltage by 90 degrees, the two branch currents are exactly 180 degrees out of phase. When these two currents sum at the main nodes, they perfectly cancel each other out. Since the external source sees zero net current flowing into the network for a given applied voltage, Ohm's law ($Z = V/I$) dictates that the impedance must be at its maximum. For deeper mathematical proofs on phase cancellation, refer to the All About Circuits textbook section on parallel tank circuits.
How do parasitic resistance and component Q-factor affect a parallel tuned circuit?
Parasitic resistance (primarily the DC resistance of the inductor's wire) is the enemy of a high-Q parallel tank. The Quality factor (Q) of a parallel circuit is defined by the ratio of the equivalent parallel resistance to the inductive reactance ($Q = R_p / X_L$). High parasitic resistance lowers $R_p$, which directly lowers the Q-factor. A low Q-factor results in a wider, flatter bandwidth and a lower peak impedance, making the circuit less effective at rejecting narrow bands of noise or sustaining oscillation in RF transmitter designs. When designing high-Q tanks, always select inductors with the lowest possible DC resistance and use air-core or high-frequency ferrite materials to minimize core losses, as detailed in Electronics Tutorials.
