The Core Physics: Formula for Capacitance of a Parallel Plate Capacitor
When designing capacitive sensors, bypass networks, or custom RF structures, you cannot rely on off-the-shelf component bins. You have to build the capacitor into the physical layout of your PCB or enclosure. The governing equation is the formula for capacitance of a parallel plate capacitor:
C = (ε₀ · εᵣ · A) / d
Where:
- C = Capacitance in Farads (F)
- ε₀ = Permittivity of free space (8.854 × 10⁻¹² F/m)
- εᵣ = Relative permittivity (dielectric constant) of the material between plates
- A = Overlapping area of the plates in square meters (m²)
- d = Distance between the plates in meters (m)
Let us run a concrete numeric example. Suppose you are designing a liquid-level sensor using standard 1.6mm thick FR4 fiberglass (εᵣ ≈ 4.5) as the dielectric, with a copper pour on the top layer and a ground plane on the bottom layer. If you need a baseline capacitance of 10 pF (10 × 10⁻¹² F) to interface with a microcontroller's touch peripheral, we can solve for the required area (A):
A = (10 × 10⁻¹² F × 1.6 × 10⁻³ m) / (8.854 × 10⁻¹² F/m × 4.5)
A ≈ 0.000401 m², or 4.01 cm².
This means a square copper pad measuring exactly 20mm × 20mm on a standard 1.6mm FR4 board will yield your target 10 pF. For deeper physics references on how dielectric polarization affects this baseline, consult the Georgia State University HyperPhysics capacitor database.
Circuit Topology and Node Definitions
A raw capacitor is useless without a readout topology. For a parallel-plate proximity or touch sensor, we use an RC charge-transfer topology. Here is the node mapping for our circuit:
- Node 1 (VCC): 3.3V supply rail.
- Node 2 (Sense): The 20×20mm parallel plate capacitor (C_sense), connected to the microcontroller's high-impedance input (e.g., ESP32 GPIO 4).
- Node 3 (GND): The reference ground plane acting as the second plate of the capacitor.
- R1 (Pull-up/Charge Resistor): A 1 MΩ resistor connecting Node 1 to Node 2, establishing the RC time constant.
Behavior Matrix: Tuning the Physical Variables
When you alter the physical geometry or the dielectric material, the electrical behavior shifts predictably. Here is what happens to the circuit when you change one variable while holding the others constant.
| Variable Changed | Effect on C_sense | Effect on RC Time Constant (τ) | Effect on ESP32 Touch Reading |
|---|---|---|---|
| Increase Area (A) | Increases linearly | Charge time increases | Baseline reading drops (higher capacitance) |
| Increase Distance (d) | Decreases inversely | Charge time decreases | Baseline reading rises (lower capacitance) |
| Insert High-εᵣ Dielectric (e.g., Water) | Increases massively (Water εᵣ ≈ 80) | Charge time spikes | Triggers touch interrupt (massive drop in reading) |
| Decrease R1 Value | No change to C | Charge time decreases | Faster sampling rate, but lower resolution |
Design Walkthrough: Sizing the Plates and Pull-Up Resistor
Let us design a complete readout circuit for our 10 pF parallel plate sensor using an external RC charge-time measurement (useful if your MCU lacks internal touch peripherals). We will target an RC time constant (τ) that a standard 1 MHz hardware timer can easily resolve.
- Fix the Capacitor: We established C = 10 pF based on a 20×20mm pad over 1.6mm FR4.
- Select the Resistor (R1): We want a τ of roughly 10 µs to allow for 100+ samples per second without aliasing. Using τ = R × C, we get R = 10 µs / 10 pF = 1 MΩ.
- Component Selection: Use a 1 MΩ, 1% tolerance metal film resistor (e.g., Yageo MFR-25FBF52-1M). Carbon composition resistors will introduce excess thermal noise that disrupts the high-impedance Node 2.
- MCU Configuration: Set the microcontroller GPIO to output LOW to discharge the plate, then switch to high-impedance INPUT and start the hardware timer. Measure the time it takes for Node 2 to cross the MCU's logical HIGH threshold (typically ~0.7 × VCC).
Decision Path: Choosing Your Readout Topology
Do not default to a 555 timer just because it is familiar. Use this decision tree to select the correct readout IC or microcontroller peripheral for your parallel plate design.
| Application Scenario | Recommended Topology | Concrete Part / Pin Pick |
|---|---|---|
| Measuring liquid level through a 3mm plastic tank wall | MCU Internal Charge-Transfer Touch Peripheral | ESP32-WROOM-32E, GPIO 4 (T0) |
| High-speed proximity detection in a noisy industrial VFD environment | Relaxation Oscillator feeding a Schmitt Trigger | LM311 Comparator + 74HC14 |
| Basic educational prototyping on a solderless breadboard | Astable Multivibrator | NE555P (TI) with 10kΩ/1MΩ network |
Default Recommendation: For 90% of modern DIY and commercial IoT designs, terminate your decision path at the ESP32 internal touch peripheral. It eliminates the need for R1, reduces BOM cost, and handles the charge-transfer timing in silicon. Consult the Espressif ESP-IDF Touch Pad API documentation for exact threshold calibration routines.
Failure Modes at the Extremes: Open and Short Circuits
Understanding what breaks when the physical geometry fails is critical for designing robust fault-detection routines in your firmware.
The Open Extreme (d → ∞ or Trace Break)
If the connection between Node 2 and the microcontroller breaks, or if the ground plane (Node 3) is entirely removed, the capacitance approaches zero. More dangerously, Node 2 becomes a floating, high-impedance antenna. It will couple with 50/60Hz mains hum in the room. The failure signature: The ESP32 touch reading will saturate at its maximum integer limit, or the external RC timer will throw a timeout error because the voltage never reaches the logic HIGH threshold.
The Short Extreme (d → 0)
If your PCB manufacturing house creates a solder bridge between the 20×20mm sense pad and the ground via, or if the dielectric breaks down and the plates physically touch, d becomes zero. The capacitance becomes effectively infinite (a dead short to ground). The failure signature: If using an external 1 MΩ pull-up, Node 2 will be pinned at 0V. The microcontroller will read a continuous logic LOW, and the RC timer will read 0 µs. If using the ESP32 internal touch peripheral, the hardware state machine will flag a TOUCH_PAD_ERR because the internal current source cannot charge a shorted node.
Breadboard Verification and Final Topology Verdict
You cannot easily mill a 1.6mm FR4 parallel plate on a solderless breadboard, but you can verify the formula and the RC timing using two bare copper-clad PCB scraps before committing to a final layout.
- Prepare the Plates: Cut two 20mm × 20mm squares of single-sided copper clad board.
- Set the Dielectric Gap: Place a standard 1.6mm thick piece of bare FR4 (no copper) between them to act as the dielectric. Clamp them together with a plastic binder clip.
- Wire the Topology: Solder a 30 AWG wire to the top plate (Node 2) and the bottom plate (Node 3). Connect Node 3 to your breadboard GND rail.
- Insert R1: Plug a 1 MΩ resistor into the breadboard, connecting the 3.3V rail to Node 2.
- Measure with an Oscilloscope: Connect your scope probe to Node 2. Trigger on the rising edge. You should see an RC charge curve reaching 63.2% of 3.3V (approx 2.08V) in exactly 10 µs.
- Test the Formula: Slide a piece of thin plastic (like a blister pack, εᵣ ≈ 3.0) between the plates, replacing the FR4. Watch the time constant drop on the scope, confirming the inverse relationship between C and the dielectric constant in the formula.
Why Parallel Plate Over Interdigitated or Cylindrical?
You might see interdigitated (comb-like) capacitors used in surface-mount humidity sensors, or cylindrical capacitors in coaxial cables. We choose the parallel plate topology for proximity and touch sensing because the electric field is highly uniform and confined between the plates. Interdigitated sensors rely entirely on fringe fields extending into the air; their capacitance is highly susceptible to surface condensation, dust, and finger oils, and their math requires complex empirical finite-element analysis rather than a clean algebraic formula. Cylindrical topologies are excellent for shielding but impossible to fabricate into flat enclosure walls or PCBs.
When you need a predictable, calculable baseline capacitance that responds linearly to a target approaching a flat surface, the parallel plate topology—sized precisely via C = (ε₀ · εᵣ · A) / d—is the definitive engineering choice.
