A parallel LR circuit consists of a resistor (R) and an inductor (L) connected across the same two nodes, meaning both components share the exact same voltage potential. Unlike series configurations where current is constant and voltage divides, a parallel LR topology forces the source current to split into two distinct branches: a purely resistive branch and a purely inductive branch. The total current is the phasor sum of these two branch currents, resulting in a total current that lags the source voltage by an angle between 0° and 90°.

This topology is foundational in AC filter networks, phase-shift oscillators, and snubber circuits. Below, we break down the node behavior, contrast it with series alternatives, select real-world components, and outline a bench-testing procedure that accounts for common measurement traps.

The Parallel LR Topology and Node Behavior

In a standard parallel LR configuration, we define two primary nodes:

  • Node A (Top Rail): The common connection point tied to the AC source's positive/live terminal.
  • Node B (Bottom Rail): The common connection point tied to the AC source's negative/neutral or ground reference.

Because both the resistor and inductor bridge Node A and Node B, the voltage across both is identical ($V_R = V_L = V_{source}$). However, the currents behave differently. The resistive current ($I_R$) is perfectly in phase with the voltage, while the inductive current ($I_L$) lags the voltage by exactly 90°. The total impedance ($Z$) is not a simple arithmetic sum, but a product-over-phasor-sum calculation.

Behavior Matrix: Element Variation Effects

Understanding how the circuit reacts when you swap component values is critical for tuning filters. Here is what happens when you alter one element while holding the AC source frequency and voltage constant:

Component Change Effect on Total Impedance (Z) Effect on Phase Angle (Current Lag) Effect on Branch Currents
Increase Resistance (R) Increases (approaches $X_L$) Increases (approaches 90° lag) $I_R$ drops; $I_L$ remains unchanged
Decrease Resistance (R) Decreases (approaches R) Decreases (approaches 0° lag) $I_R$ rises; $I_L$ remains unchanged
Increase Inductance (L) Increases (approaches R) Decreases (approaches 0° lag) $I_L$ drops; $I_R$ remains unchanged
Increase Frequency (f) Increases (approaches R) Decreases (approaches 0° lag) $I_L$ drops; $I_R$ remains unchanged

Parallel vs. Series LR: Failure Modes and Topology Choice

Why choose a parallel LR circuit over a series LR circuit? The decision hinges on how you want the circuit to handle branch independence and fault conditions. In a series LR circuit, a single component failure interrupts the entire current path. In a parallel LR topology, the branches operate independently, which is vital in applications like multi-way audio crossover networks or parallel snubber paths where one branch must continue functioning if the other degrades.

Extreme Failure Mode Contrast

When designing for reliability, you must analyze what happens at the extremes (opens and shorts). Here is the failure-mode contrast between the two topologies:

  • Resistor Shorts: In a series circuit, a shorted resistor leaves only the inductor in the path (high impedance at AC, low at DC). In a parallel circuit, a shorted resistor creates a dead short across Node A and Node B, instantly tripping the breaker or blowing the source fuse.
  • Resistor Opens: In a series circuit, an open resistor breaks the entire circuit (zero current). In a parallel circuit, the resistor branch simply drops out, and the circuit becomes a pure inductor (current lags by exactly 90°).
  • Inductor Shorts: In a series circuit, a shorted inductor leaves only the resistor (purely resistive, 0° phase shift). In a parallel circuit, a shorted inductor acts as a dead short across the source, destroying the power supply if unprotected.
  • Inductor Opens: In a series circuit, an open inductor kills all current flow. In a parallel circuit, the inductor branch drops out, leaving a purely resistive load (0° phase shift).
Callout Tip: Because a short in either parallel branch results in a dead short across the AC source, parallel LR circuits used in mains or high-current applications must always be protected by a properly sized fast-acting fuse on the main feeder line before Node A.

Design Walkthrough: Selecting Real Component Values

Let us design a parallel LR circuit intended to act as a phase-shift network at a target frequency of 1 kHz. We want a total impedance magnitude of roughly 50Ω to match a standard signal generator output, and we need a significant phase shift.

1. Select the Inductor (L)
We choose a 10 mH radial shielded inductor (e.g., Bourns 78F100J-RC). This part has a DC resistance (DCR) of roughly 0.7Ω, which is low enough to ignore for our 1 kHz AC calculations, and a self-resonant frequency well above our 1 kHz target.

2. Calculate Inductive Reactance ($X_L$)
At 1 kHz, the reactance is:
$X_L = 2 \pi f L = 2 \times 3.14159 \times 1000 \times 0.01 = 62.83 \Omega$

3. Select the Resistor (R)
To create a balanced phase shift, we want the resistance to be in the same ballpark as the reactance. We select a standard 100Ω 1/4W carbon film resistor (e.g., Yageo CFR-25JR-52-100R).

4. Calculate Total Impedance and Phase Angle
The total impedance magnitude for a parallel LR circuit is calculated using the admittance method:
$Z = \frac{R \times X_L}{\sqrt{R^2 + X_L^2}} = \frac{100 \times 62.83}{\sqrt{100^2 + 62.83^2}} = \frac{6283}{\sqrt{10000 + 3947.6}} = \frac{6283}{118.1} = 53.2 \Omega$

The phase angle ($\theta$) by which the total current lags the voltage is:
$\theta = \arctan\left(\frac{R}{X_L}\right) = \arctan\left(\frac{100}{62.83}\right) = \arctan(1.59) = 57.8^\circ$

With a 12V RMS source at 1 kHz, the total current drawn will be $I = V / Z = 12 / 53.2 = 225$ mA, lagging the voltage by 57.8°. The resistive branch draws 120 mA (in-phase), and the inductive branch draws 191 mA (lagging by 90°). The phasor sum of 120 mA and 191 mA yields the 225 mA total.

Step-by-Step Breadboard Testing Procedure

Testing AC circuits on a breadboard introduces parasitic capacitance and source-impedance errors. Follow these steps to accurately verify your parallel LR design using a function generator and an oscilloscope.

  1. Verify Component Baselines: Before inserting components, use a multimeter to measure the actual DC resistance of the 100Ω resistor. Then, measure the DCR of the 10mH inductor. If the inductor's DCR is higher than expected (e.g., >5Ω), it will skew your low-frequency phase measurements.
  2. Wire Node A and Node B: Insert the resistor and inductor into the breadboard so that both of their left leads share a single 5-hole row (Node A) and both right leads share another 5-hole row (Node B). Use 22 AWG solid jumper wires to keep parasitic inductance low.
  3. Configure the Function Generator: Set your function generator to output a 1 kHz sine wave at 2V peak-to-peak. Critical Step: Ensure the generator's output impedance is set to High-Z (or account for the default 50Ω output impedance). If your generator has a 50Ω internal impedance and you drive a 53Ω parallel LR load, the voltage at Node A will drop by nearly half due to the internal voltage divider effect.
  4. Probe the Voltage (Channel 1): Connect Oscilloscope Channel 1 across Node A and Node B. Verify the sine wave is clean and measure the exact Vpp and frequency.
  5. Measure the Current Phase (Channel 2): To measure the total current phase, you must insert a small shunt resistor (e.g., 1Ω) in series with the main feeder line before Node A. Connect Channel 2 across this shunt resistor. The voltage across the shunt represents the total current. Measure the time delay ($\Delta t$) between the zero-crossings of Ch1 (Voltage) and Ch2 (Current). Calculate the phase shift: $\theta = \Delta t \times f \times 360^\circ$. It should read close to 57.8°.
Bench Gotcha: If your measured phase shift is significantly lower than 57.8°, your inductor is likely saturating or exhibiting high core losses at 1 kHz. Ferrite-core inductors optimized for high-frequency RF (like the Bourns 78F series) handle 1 kHz well, but iron-powder cores meant for 100 kHz+ switching supplies will exhibit severe hysteresis losses at audio frequencies, acting more like a resistor than an inductor.

Parallel LR Circuit FAQ

How do you calculate the total impedance of a parallel LR circuit?

You cannot simply add the resistance and reactance. Because the currents are 90° out of phase, you must calculate the admittance (Y) first. The conductance is $G = 1/R$ and the inductive susceptance is $B_L = 1/X_L$. The total admittance magnitude is $Y = \sqrt{G^2 + B_L^2}$. The total impedance is simply the reciprocal: $Z = 1/Y$. Alternatively, use the product-over-phasor formula: $Z = (R \times X_L) / \sqrt{R^2 + X_L^2}$.

What happens to the phase angle in a parallel LR circuit at high frequencies?

As frequency increases, the inductive reactance ($X_L = 2\pi fL$) increases proportionally. This means the inductor draws less current, while the resistor's current remains constant. Consequently, the total current becomes dominated by the resistive branch, and the phase angle decreases, approaching 0° (purely resistive). Conversely, at very low frequencies, $X_L$ drops toward zero, the inductor dominates, and the phase angle approaches 90°.

Can I use a parallel LR circuit as a bandpass filter?

Not on its own. A basic parallel LR circuit acts as a low-pass filter when the output is taken across the components, or a high-pass filter if configured differently in a network. To create a bandpass filter, you need a resonant tank circuit, which requires adding a capacitor in parallel (creating a parallel RLC circuit) or placing the parallel LR network in series with a capacitor. For deep dive into RLC filter topologies, refer to standard AC network analysis resources like All About Circuits.

Why does my parallel LR circuit draw more current than expected on the bench?

If your measured total current exceeds your theoretical calculations, the most common culprit is inductor core saturation or unaccounted DC bias. If your AC signal has a DC offset, the inductor core may saturate, causing its effective inductance to plummet. A lower inductance means a lower $X_L$, which causes the inductive branch to draw massive amounts of current. Always use an oscilloscope to verify your function generator is outputting a pure AC signal with 0V DC offset, and consult the manufacturer's datasheet for the inductor's saturation current ($I_{sat}$) rating.

Where can I find reliable reference data for AC parallel circuit math?

For comprehensive formulas, phasor diagrams, and worked examples regarding parallel AC networks, the Electronics Tutorials parallel AC circuits guide provides excellent visual breakdowns of the admittance triangle and current phasors that supplement the math provided in this walkthrough.