The standard non-inverting opamp circuit diagram uses a resistive feedback network to set a precise closed-loop voltage gain while maintaining an exceptionally high input impedance. Unlike the inverting configuration, the input signal is applied directly to the non-inverting (+) terminal, meaning the output signal preserves the phase of the input. For a target gain of 11, you will use a 10 kΩ feedback resistor and a 1 kΩ ground resistor. This topology is the default choice for sensor buffering, audio pre-amplification, and impedance matching where loading the source circuit must be avoided.
The Non-Inverting Opamp Circuit Diagram: Topology & Node Labels
To analyze or build this circuit, you must first map the physical pins of the integrated circuit to the schematic nodes. Using a standard dual op-amp like the Texas Instruments TL072 or LM358, the topology relies on six critical nodes:
- Node 1 (V+ / Non-Inverting Input): The high-impedance input where your signal source connects. Ideal op-amps draw zero current here; real JFET op-amps like the TL072 draw roughly 50 pA.
- Node 2 (V- / Inverting Input): The summing junction. The feedback network connects here. Due to the op-amp's high open-loop gain, this node acts as a 'virtual short' to Node 1, tracking the input voltage exactly.
- Node 3 (Vout / Output): The driven terminal that sources or sinks current to the load and the feedback network.
- Node 4 (VCC / V+ Supply): The positive power rail (e.g., +9V or +15V).
- Node 5 (VEE / V- Supply): The negative power rail (e.g., -9V or -15V) or system ground in single-supply designs.
- Node 6 (Feedback Divider Node): The junction between the feedback resistor ($R_f$) and the ground resistor ($R_g$), physically wired to Node 2.
Why Non-Inverting Over Inverting? (And When to Switch)
Choosing between the non-inverting and inverting topologies dictates how your source circuit behaves. The decision almost always comes down to input impedance and phase requirements.
| Criterion | Non-Inverting Topology | Inverting Topology |
|---|---|---|
| Input Impedance | Extremely high (10⁶ to 10¹² Ω, depending on IC) | Equal to the input resistor ($R_{in}$), often 1kΩ - 10kΩ |
| Phase Relationship | 0° shift (Output is in phase with Input) | 180° shift (Output is inverted) |
| Minimum Voltage Gain | 1 (Unity gain, acts as a voltage follower) | 0 (Can attenuate signals below unity) |
| Common Mode Voltage | Equals the input signal (requires good CMRR) | Virtual ground (0V, ignores op-amp CMRR limits) |
| Best Application | Piezoelectric sensors, electret mics, high-Z buffers | Summing mixers, active filters, DAC current-to-voltage |
You choose the non-inverting opamp circuit diagram when your source cannot supply meaningful current. For example, a piezoelectric vibration sensor generates high voltage but virtually zero current. If you use an inverting amplifier with a 10 kΩ input resistor, you will load the sensor and collapse its signal. The non-inverting topology's megaohm-level input impedance prevents this loading effect. Conversely, if you need to sum multiple audio signals or attenuate a 5V DAC output down to a 3.3V ADC range, the inverting topology is mathematically superior.
Design Walkthrough: Building a Gain-of-11 Amplifier
Let's design a practical DC-coupled amplifier with a voltage gain ($A_v$) of 11 using a TL072CP JFET-input dual op-amp. We will use a dual ±9V power supply to allow the output to swing symmetrically above and below 0V without needing complex DC biasing networks.
The Gain Formula:
$$A_v = 1 + \frac{R_f}{R_g}$$
Component Selection:
- Op-Amp: TL072CP (Low noise, JFET inputs, ±9V to ±15V nominal supply range).
- Feedback Resistor ($R_f$): 10 kΩ (1% metal film). Keeps current draw low while staying well below the threshold where thermal noise and parasitic PCB capacitance become problematic (>100 kΩ).
- Ground Resistor ($R_g$): 1 kΩ (1% metal film). Yields $1 + (10,000 / 1,000) = 11$.
- Decoupling Capacitors: Two 100 nF (0.1 µF) X7R ceramic capacitors. One from VCC to Ground, one from VEE to Ground, placed within 5 mm of the IC power pins.
If you inject a 100 mV peak sine wave at 1 kHz into Node 1, Node 2 will track at 100 mV. The current through $R_g$ is $I = V / R = 0.1V / 1000\Omega = 100 \mu A$. Because the inverting input draws no current, that same 100 µA must flow through $R_f$, creating a 1V drop across it. The output (Node 3) sits at $V_{in} + V_{Rf} = 0.1V + 1.0V = 1.1V$. The math holds perfectly on the bench.
Behavior Matrix: Component Drift and Failure Extremes
Understanding what happens when components fail or drift separates theoretical designers from bench engineers. Here is the failure-mode contrast for the non-inverting topology.
| Component | Condition / Fault | Effect on Circuit Behavior | Resulting Output State |
|---|---|---|---|
| $R_f$ (Feedback) | Drifts +5% (Heat/Age) | Gain increases slightly to 11.55 | Minor amplitude error |
| $R_f$ (Feedback) | Opens (Broken solder joint) | Feedback loop breaks; open-loop gain takes over | Output slams to VCC or VEE rail (Comparator mode) |
| $R_f$ (Feedback) | Shorts to output | $R_f$ becomes 0Ω; Gain equation becomes $1 + 0$ | Acts as unity-gain buffer (Gain = 1) |
| $R_g$ (Ground) | Opens (Lifted pad) | Denominator in gain equation goes to 0 | Output slams to VCC or VEE rail (Saturation) |
| $R_g$ (Ground) | Shorts to ground | $R_g$ becomes 0Ω; all feedback current bypasses | Acts as unity-gain buffer (Gain = 1) |
| Op-Amp IC | Input stage ESD damage | Input bias current spikes to microamps | Massive DC offset voltage at output |
Notice the asymmetry in failure modes: an open in the feedback path causes chaotic rail-saturation, while a short in the feedback path safely defaults the circuit to a unity-gain buffer. When designing for harsh environments, placing a high-value backup resistor (e.g., 1 MΩ) in parallel with $R_g$ can prevent an open-fault from causing total system saturation.
Step-by-Step Breadboard Testing & Verification
Breadboarding high-gain op-amp circuits often results in high-frequency oscillation if layout rules are ignored. Follow this exact sequence to verify your opamp circuit diagram on a solderless prototyping board.
- Seat the IC and Route Power: Place the TL072 across the center trench. Connect VCC (Pin 8) to the +9V rail and VEE (Pin 4) to the -9V rail. Do not apply power yet.
- Install Decoupling Capacitors: Jam a 100 nF ceramic capacitor directly across the +9V rail and the ground rail, physically adjacent to Pin 8. Repeat for the -9V rail and ground near Pin 4. Skipping this step guarantees oscillation above 100 kHz.
- Build the Feedback Network: Insert $R_g$ (1 kΩ) from Pin 1 (Inverting Input) to the ground rail. Insert $R_f$ (10 kΩ) from Pin 1 to Pin 7 (Output). Keep the physical distance between these components under 1 cm to minimize the feedback loop area.
- Connect the Source and Load: Wire your function generator's BNC shield to the breadboard ground, and the center conductor to Pin 3 (Non-Inverting Input). Connect your oscilloscope probe tip to Pin 7, and the probe ground clip to the breadboard ground.
- Power Up and Verify DC: Turn on the dual power supply. With no AC signal applied, measure the DC voltage at Pin 7 with a multimeter. It should read between -15 mV and +15 mV (the TL072's typical input offset voltage multiplied by the gain of 11). If it reads ±8V, your feedback network is open.
- Inject AC and Measure Gain: Set the function generator to a 1 kHz sine wave, 200 mV peak-to-peak. Trigger the oscilloscope on Channel 1 (Input). Measure Channel 2 (Output). You should see a 2.2V peak-to-peak sine wave, perfectly in phase with Channel 1.
Opamp Circuit Diagram FAQs
How do I add a DC offset to an opamp circuit diagram?
To shift the output voltage up or down without affecting the AC gain, inject a reference voltage into the non-inverting input alongside your AC signal. Use a resistive voltage divider from your VCC rail to ground to create a stable DC bias (e.g., 2.5V). Pass this bias through a low-pass RC filter (e.g., 10 kΩ and 10 µF) to eliminate power supply ripple, then AC-couple your actual signal into that same node using a series capacitor (e.g., 1 µF film capacitor). The op-amp will amplify the AC signal while the DC bias sets the new 'zero' reference point at the output.
Why is my opamp circuit diagram oscillating on the breadboard?
Oscillation in a non-inverting configuration is almost always caused by parasitic capacitance at the inverting input (Node 2) combined with inadequate power supply decoupling. Solderless breadboards introduce roughly 2 pF to 5 pF of stray capacitance between adjacent rows. When combined with a high-value feedback resistor (e.g., >100 kΩ), this creates an unintended low-pass filter in the feedback path, introducing phase lag that eats into the op-amp's phase margin. To fix this, drop your resistor values into the 1 kΩ - 10 kΩ range, add a small compensation capacitor (10 pF to 100 pF) in parallel with $R_f$, and ensure 100 nF ceramic decoupling capacitors are touching the IC's power pins.
Can I use a single-supply opamp circuit diagram for AC audio signals?
Yes, but you must artificially create a 'virtual ground' at half your supply voltage (VCC/2). Standard op-amps cannot output negative voltages if their VEE pin is tied to 0V. If you feed an AC audio signal swinging below 0V into a single-supply circuit, the negative half-cycles will be hard-clipped at 0V, causing severe distortion. Use a rail-splitter IC like the TLE2426, or a buffered voltage divider, to establish a VCC/2 bias node. Tie your ground resistors and the input signal's return path to this virtual ground instead of the physical 0V battery terminal. For high-fidelity audio, however, a true dual-rail supply (±12V or ±15V) remains vastly superior as it eliminates the need for bulky DC-blocking output capacitors.
References and further reading: Texas Instruments LM358/LM358A Datasheet; All About Circuits: Introduction to Operational Amplifiers; Analog Devices MT-031 Tutorial: Grounding and Decoupling Op Amps.
