The NOT gate (inverter) outputs the exact logical complement of its input: a HIGH (1) input yields a LOW (0) output, and vice versa. Whether you are reading a schematic or probing a physical breadboard, recognizing the NOT logic gate symbol and understanding its physical IC pinout is foundational to digital design. Below is the complete reference for schematic symbols, truth tables, and physical 14-pin DIP integrated circuits used in 2026 bench work.
NOT Logic Gate Symbol and Truth Table Reference
Schematic symbols for logic gates vary depending on the standard your region or company adheres to. In the US, the ANSI/IEEE 91-1984 standard dominates, while European and international designs typically follow IEC 60617. The defining feature of any NOT gate symbol is the inversion bubble (a small circle) on the output line.
| Standard | Symbol Shape | Inversion Marker | Boolean Expression | Truth Table (A → Y) |
|---|---|---|---|---|
| ANSI/IEEE 91 | Right-pointing triangle | Bubble on output tip | Y = A' or Y = ¬A | 0 → 1 | 1 → 0 |
| IEC 60617 | Rectangular box | Small circle on output | Y = NOT A | 0 → 1 | 1 → 0 |
| DIN (Legacy) | Triangle with flat back | Bubble on output tip | Y = A̅ | 0 → 1 | 1 → 0 |
| Hardware (Buffer) | Triangle (no bubble) | None (Non-inverting) | Y = A | 0 → 0 | 1 → 1 |
What the bubble means in practice: The bubble represents logical negation. When you see a bubble on the input of an AND or OR gate, it means that specific input is "active-low." However, on a standalone NOT gate, the bubble is strictly on the output, indicating that the signal leaving the gate is the inverse of the signal entering it.
Standard IC Pinouts: 7404, 74HC04, and CD4049
On the bench, you will rarely wire discrete transistors to build an inverter. Instead, you will use a hex inverter IC, which packs six independent NOT gates into a single 14-pin Dual In-line Package (DIP). The physical pinout for almost all 14-pin hex inverters follows the same layout: Pin 14 is VCC (Power), Pin 7 is GND (Ground), and the remaining pins form six input/output pairs (1A→1Y, 2A→2Y, etc.).
| Part Number | Logic Family | VCC Range | Propagation Delay | Special Characteristics | Approx. 2026 Price (DIP-14) |
|---|---|---|---|---|---|
| SN7404 | TTL (Bipolar) | 4.75V - 5.25V | ~12 ns | Legacy; high power draw, strict 5V requirement | $0.85 - $1.20 |
| SN74HC04 | CMOS (High-Speed) | 2.0V - 6.0V | ~14 ns @ 5V | Industry standard; low static power, wide voltage | $0.15 - $0.35 |
| CD4049UB | CMOS (4000 Series) | 3.0V - 18.0V | ~60 ns @ 5V | High-voltage input tolerance; unbuffered output | $0.40 - $0.65 |
| SN74HC14 | CMOS (Schmitt) | 2.0V - 6.0V | ~15 ns @ 5V | Hysteresis on inputs; rejects noisy/slow signals | $0.20 - $0.40 |
Pin Mapping (Standard 14-Pin DIP):
- Pin 14: VCC (Positive Supply)
- Pin 7: GND (Ground)
- Gate 1: Input = Pin 1, Output = Pin 2
- Gate 2: Input = Pin 3, Output = Pin 4
- Gate 3: Input = Pin 5, Output = Pin 6
- Gate 4: Input = Pin 9, Output = Pin 8
- Gate 5: Input = Pin 11, Output = Pin 10
- Gate 6: Input = Pin 13, Output = Pin 12
For deep-dive schematic and electrical characteristics, refer to the Texas Instruments SN74HC04 Datasheet or the onsemi CD4049UB specification sheet.
Never leave an unused input pin floating on a 74HC04 or CD4049. Unlike older TTL chips, CMOS inputs have extremely high impedance. A floating pin will act as an antenna, picking up ambient electromagnetic noise and rapidly switching the internal PMOS/NMOS transistor pairs. This causes massive shoot-through current, leading to thermal runaway and a melted IC. Always tie unused inputs to VCC or GND via a 10kΩ resistor.
Rows People Get Wrong and Faded Marking Recovery
When reading schematics or scavenging parts from old PCBs, a few specific pitfalls routinely trap hobbyists and junior engineers.
The 'Rows People Get Wrong' Notes
- Confusing the 4049UB with the 4069: Both are CMOS hex inverters, but the CD4049UB is unbuffered and designed to accept input voltages higher than its VCC (useful for level shifting). The CD4069 is buffered and will latch up or suffer gate oxide breakdown if an input exceeds VCC. Do not substitute them blindly.
- Misreading the Inversion Bubble: In ANSI schematics, if a bubble is placed on the input of a flip-flop or an AND gate, it does not mean a NOT gate is physically present. It denotes an "active-low" trigger. The physical IC used might just be a standard 7408 AND gate, not a 7404 inverter feeding it.
- Schmitt Trigger vs. Standard Inverter: If your input signal is a slow-rising analog wave (like a sine wave from a sensor or a noisy mechanical switch), a standard 74HC04 will oscillate violently at the threshold voltage. You must use the 74HC14 (Schmitt-trigger inverter), which features built-in hysteresis to provide clean digital edges.
Safe Interpretation When IC Markings are Faded
Scavenging DIP chips from damaged boards often means dealing with laser etching that has been burned off or scraped away. If you have an unmarked 14-pin IC and suspect it is a hex inverter, follow this safe bench recovery procedure:
- Identify VCC and GND: Set your multimeter to continuity/diode mode. Probe Pin 7 against a known ground plane, and Pin 14 against the positive rail. If Pin 14 shows a diode drop (~0.6V) to Pin 7, you have confirmed power orientation.
- Apply Safe Power: Power the IC with 5.0V DC. Do not exceed 5V until you confirm it is not a legacy 7400-series TTL chip, which will instantly die at 7V+.
- Probe for Inversion: Use a logic probe or a multimeter in DC voltage mode. Tie Pin 1 to GND (0V). Measure Pin 2. If Pin 2 reads ~5V (HIGH), you have confirmed an inverter. Repeat for Pin 3 (Input) and Pin 4 (Output).
- Check for Schmitt Hysteresis: If you need to know if it is a 74HC04 or a 74HC14, connect a 10kΩ potentiometer to the input. Slowly sweep the voltage from 0V to 5V while monitoring the output. A standard 74HC04 will flip states at exactly ~2.5V. A 74HC14 will flip HIGH at ~3.1V, and require you to drop the voltage down to ~1.9V before it flips back LOW.
Understanding the NOT logic gate symbol is only the first step; mastering the physical realities of propagation delay, input capacitance, and family-specific voltage thresholds is what separates a working breadboard prototype from a reliable, production-ready digital circuit.
