The NOT gate (inverter) has two primary schematic symbols in active use today: the ANSI/IEEE distinctive shape (a triangle with an inversion bubble) and the IEC 60617 rectangular outline (a rectangle with a right-side negation circle). Below is the master reference for identifying, interpreting, and sourcing these components across global standards.
Master NOT Gate Symbol & Logic Reference
This table maps the logical function to its visual representations across the three dominant schematic standards. Use this to decode legacy military prints, modern European industrial panels, and standard North American academic schematics.
| Standard / Region | Symbol Name | Visual Description | Primary Use Case |
|---|---|---|---|
| ANSI/IEEE Std 91 (North America) | Distinctive Shape | Right-pointing triangle with a small circle (bubble) on the output apex. | Academia, hobbyist schematics, US commercial electronics. |
| IEC 60617-12 (Europe / Global) | Rectangular Outline | Rectangle with the qualifier "1" inside and a negation circle on the right edge. | Industrial automation, PLC logic diagrams, EU regulatory filings. |
| MIL-STD-806 (Legacy US Military) | Military Distinctive | Identical to ANSI distinctive shape, but often drawn with sharper angles and strict grid alignment. | Aerospace, legacy defense schematics (superseded by IEEE 91). |
| Schmitt-Trigger Variant (Universal) | Hysteresis Inverter | Standard triangle/rectangle containing a hysteresis loop (a squiggly line resembling a tilted 'S' or square wave). | Signal conditioning, debouncing switches, noise rejection. |
The Logic Truth Table
Regardless of the visual standard used on the schematic, the underlying boolean logic remains identical. The output is always the logical complement of the input.
| Input (A) | Output (Y) | Boolean Expression |
|---|---|---|
| 0 (LOW) | 1 (HIGH) | Y = A' (or Y = ¬A) |
| 1 (HIGH) | 0 (LOW) |
Rows People Get Wrong & Faded Marking Interpretation
When reading complex schematics or troubleshooting faded PCB silkscreens, the inversion bubble is the most frequently misinterpreted element. Here is how to avoid common bench mistakes.
The "Rows People Get Wrong" Notes
- The Bubble Means "Active-Low", Not Always "NOT": When you see an inversion bubble on the input side of a flip-flop or microcontroller pin (like an active-low RESET or Chip Enable), it does not mean there is a discrete NOT gate in the circuit. It indicates that the internal logic triggers when the signal drops to 0V. Do not go looking for a 74HC04 IC that isn't there.
- Double Negation (Bubbles on Both Ends): If a signal line has a bubble on the output of Gate A, and a bubble on the input of Gate B, they cancel each other out logically. In practice, this is often drawn to maintain "active-low" signal naming conventions across a bus, rather than indicating two physical inversions.
- Missing the Hysteresis Loop: Swapping a standard 74HC04 for a 74HC14 (Schmitt-trigger) to clean up a noisy mechanical switch signal is a common fix. However, if you misread the schematic and miss the hysteresis loop inside the ANSI triangle, you might populate the board with standard inverters, resulting in erratic oscillation and chattering outputs.
On older or heavily reworked PCBs, the silkscreen outlining the IC might be faded, leaving only a generic "U3" designator. If you cannot read the part number, trace the pins. A 14-pin DIP with Pin 7 tied to GND, Pin 14 tied to VCC, and six independent input/output pairs (e.g., Pin 1 in, Pin 2 out; Pin 3 in, Pin 4 out) is almost certainly a hex inverter. Verify with a multimeter in diode-test mode to check the internal protection diodes before applying power.
Common Hex Inverter IC Pinouts & Bench Specs
NOT gates are rarely sold as single discrete components in modern logic design. They are packaged as "Hex Inverters" (six independent NOT gates in a single 14-pin DIP or SOIC package). The pinout for almost all standard 14-pin hex inverters is identical, but the internal silicon characteristics vary wildly between logic families.
| Part Number | Logic Family | VCC Range | Typ. Propagation Delay (tpd) | Input Type |
|---|---|---|---|---|
| SN74HC04 | High-Speed CMOS | 2.0V to 6.0V | 14 ns (at 5V) | Standard CMOS |
| SN74LS04 | Low-Power Schottky TTL | 4.75V to 5.25V | 9 ns (at 5V) | TTL (Bipolar) |
| CD4069UB | 4000-Series CMOS | 3.0V to 15.0V | 50 ns (at 5V) | Standard CMOS |
| SN74LS14 | Low-Power Schottky TTL | 4.75V to 5.25V | 15 ns (at 5V) | Schmitt-Trigger |
Standard 14-Pin DIP Pinout Mapping
For all four ICs listed above, the physical pinout remains constant. Locate the notch or dimple at the top of the IC to find Pin 1.
- Gate 1: Input = Pin 1, Output = Pin 2
- Gate 2: Input = Pin 3, Output = Pin 4
- Gate 3: Input = Pin 5, Output = Pin 6
- GND: Pin 7
- Gate 4: Input = Pin 9, Output = Pin 8
- Gate 5: Input = Pin 11, Output = Pin 10
- Gate 6: Input = Pin 13, Output = Pin 12
- VCC: Pin 14
Pro-Tip for CMOS (74HC / CD4000 series): Never leave unused NOT gate inputs floating. A floating CMOS input acts as an antenna, picking up ambient RF and causing the internal MOSFETs to rapidly switch between states. This draws massive quiescent current and can thermally destroy the IC. Always tie unused inputs directly to VCC or GND. (Source: Texas Instruments SN74HC04 Datasheet).
Regional Standards: Which Symbol Applies to Your Project?
Choosing the correct symbol for your schematic isn't just about personal preference; it dictates how your design is interpreted by fabricators, inspectors, and international collaborators.
North America (ANSI/IEEE Std 91-1984)
If you are designing for the US or Canadian markets, or submitting schematics to North American universities, the distinctive shape (triangle with bubble) is the undisputed standard. It is visually intuitive because the shape implies signal flow (pointing right), and the bubble clearly denotes logical inversion. Most US-based EDA tools (like Altium or KiCad default libraries) prioritize this symbol.
Europe and International (IEC 60617-12)
If your schematics will be used in European industrial automation, PLC programming, or submitted for CE marking documentation, you must use the IEC rectangular outline. The IEC standard deliberately avoids "distinctive shapes" to maintain a uniform grid-based look for complex logic arrays. The logic function is defined by the internal qualifier (a "1" for a buffer/inverter, an "&" for AND) and the negation bubble on the output line. For a deep dive into how these rectangular symbols scale to complex programmable logic, refer to the logic gate tutorials on All About Circuits.
When to Mix Standards (And When Not To)
Never mix ANSI and IEC symbols on the same schematic page. It forces the reader to context-switch and increases the likelihood of misreading an active-low enable line as a discrete inverter. If you are taking over a legacy military project that uses MIL-STD-806, treat it as ANSI/IEEE for practical purposes—the symbols are functionally identical, though the MIL standard enforces stricter grid-placement rules that modern CAD software largely ignores.
