The standard US (ANSI/IEEE) symbol for a NOT gate (inverter) is a right-pointing triangle with a small circle (bubble) on the output tip. The international (IEC 60617) symbol is a rectangle containing the number "1" with an inversion bubble on the output. In physical hardware, this logic function is most commonly mapped to 14-pin DIP hex inverter ICs like the 74HC04 or CD4049.
Complete NOT Gate Symbol & Logic IC Reference
The table below maps the schematic symbols you will encounter on blueprints and CAD software to their governing standards and the physical silicon you will solder to the board. Always verify the voltage assumptions (TTL vs. CMOS) before substituting parts.
| Standard / Component | Symbol Shape | Internal Marking | Inversion Indicator | Physical IC / Pinout Notes |
|---|---|---|---|---|
| ANSI/IEEE Std 91 | Triangle (Distinctive Shape) | None | Circle on output tip | Default in US schematics and most Altium/KiCad libraries. |
| IEC 60617-12 | Rectangle (Outline Shape) | "1" (Identity) | Circle on output line | Mandatory for European compliance and military/aerospace IEC prints. |
| MIL-STD-806 (Legacy) | Triangle or Rectangle | Varies | Circle or slash | Found on pre-1990s military avionics; slash indicates negation. |
| 74HC04 (CMOS) | N/A (Silicon) | Hex Inverter | N/A | 14-pin DIP. VCC=14, GND=7. Pairs: 1-2, 3-4, 5-6, 8-9, 10-11, 12-13. (2V-6V) |
| CD4049 (CMOS) | N/A (Silicon) | Unbuffered Hex | N/A | 16-pin DIP. VCC=1, GND=8. High-voltage tolerant up to 15V. Often used for level shifting. |
| 74LS14 (TTL) | Triangle + Hysteresis Loop | Schmitt Trigger | Circle on output tip | Contains internal hysteresis. 14-pin DIP. Requires strict 4.75V-5.25V VCC. |
Regional Standards and Faded Schematic Interpretation
Which standard applies to your region? If you are working in North America or using default settings in mainstream EDA tools like Altium Designer or KiCad, you will almost exclusively see the ANSI/IEEE distinctive-shape triangle. If you are reading schematics originating from the EU, or working on IEC-compliant industrial control panels, you must read the IEC 60617 rectangular outlines. For a deeper dive into logic gate fundamentals, refer to the All About Circuits logic gate guide.
When working on legacy equipment where the schematic is faded, the inversion bubble is often the first detail to disappear. How do you safely interpret a missing bubble? Look at the surrounding passive components. If the output trace features a pull-up resistor to VCC and drives an active-low enable pin (often marked with an overline or a slash on the destination IC), the missing gate is almost certainly a NOT gate. Furthermore, if you are looking at a 14-pin DIP IC on the board and pins 1 and 2 are routed as an input/output pair, you are looking at a hex inverter package (like the 74HC04), regardless of what the faded paper says.
Symbols and Pinouts People Get Wrong
Even experienced hobbyists and junior technicians make substitution errors when translating these symbols to physical workbench components. Here are the specific rows and symbols that cause field failures.
The Schmitt Trigger Confusion (Row 6)
The standard ANSI NOT gate symbol is just a triangle and a bubble. However, the 74LS14 and 74HC14 Schmitt-trigger inverters add a hysteresis loop (a lazy-S or square-wave symbol) inside the triangle. People frequently miss this internal marking, substitute a standard 74HC04, and then wonder why their circuit oscillates wildly. Standard inverters have a single, sharp voltage threshold (typically VCC/2). If the input signal is noisy or slowly rising (like from an RC timing circuit or a mechanical switch), a standard NOT gate will rapidly toggle on and off as the voltage crosses that threshold. The Schmitt trigger symbol explicitly tells you the IC has two thresholds (VT+ and VT-) to prevent this chatter.
IEC "1" Block vs. Buffer
In the IEC 60617 standard, a rectangle with a "1" inside and no output bubble is a non-inverting buffer. Adding the bubble makes it a NOT gate. Technicians used to the ANSI triangle sometimes misread the IEC "1" block as an AND gate or assume the "1" means "Output is always High." The "1" simply denotes the mathematical identity function (Output = Input), which is then negated by the bubble.
The Floating Input Trap (CMOS vs TTL)
Schematic symbols do not show internal transistor topology, leading to a fatal bench mistake. If you wire a 74LS04 (TTL) and leave an unused NOT gate input unconnected (floating), it will naturally pull high internally. It is noisy, but it functions. If you do the exact same thing with a 74HC04 (CMOS), the floating input acts as an antenna. The internal push-pull MOSFETs will partially turn on simultaneously, causing "shoot-through" current. The IC will oscillate at MHz frequencies, overheat, and potentially destroy the board trace. Always tie unused CMOS NOT gate inputs to VCC or GND.
NOT Gate Symbol and Application FAQ
What is the difference between a NOT gate symbol and a buffer symbol?
In the ANSI/IEEE standard, a buffer is a right-pointing triangle without the output bubble. It outputs the exact same logic state as the input (High in = High out). The NOT gate (inverter) includes the bubble, indicating logical negation (High in = Low out). In physical hardware, buffers (like the 74HC367) are used to increase current drive capability or isolate circuit stages, while NOT gates are used for logical inversion and oscillator feedback loops.
How do I wire a physical 74HC04 hex inverter IC based on the schematic symbol?
The 74HC04 contains six independent NOT gates in a single 14-pin package. Pin 14 is VCC (connect to 2V-6V DC, typically 3.3V or 5V) and Pin 7 is GND. The gates are paired as Input/Output: Pin 1 (In) / Pin 2 (Out), Pin 3 (In) / Pin 4 (Out), and Pin 5 (In) / Pin 6 (Out). The second half of the chip mirrors this: Pin 13 (In) / Pin 12 (Out), Pin 11 (In) / Pin 10 (Out), and Pin 9 (In) / Pin 8 (Out). If your schematic only uses three inverters, you must physically wire the inputs of the remaining three unused gates to GND or VCC to prevent CMOS shoot-through.
Why does my CAD software show a rectangle instead of a triangle for the NOT gate?
Your EDA software (KiCad, Altium, Eagle) is currently set to use the IEC 60617 symbol library rather than the ANSI/IEEE distinctive-shape library. In KiCad, for example, the default logic gates often use the IEC rectangular style to comply with international standards. You can change this in the symbol library manager or by selecting the ANSI alternate symbol (often denoted with an "_ANSI" suffix in the library browser) when placing the part on your schematic sheet.
Can I build a NOT gate using NAND or NOR gate symbols if I run out of inverters?
Yes, this is a standard bench workaround. If you have a spare 74HC00 (Quad 2-Input NAND) or 74HC02 (Quad 2-Input NOR), you can create a NOT gate symbol's logical equivalent by tying both inputs of a single gate together. For a NAND gate, tying Input A and Input B together means the only possible states are (0,0) which outputs 1, and (1,1) which outputs 0—perfect inversion. Alternatively, you can tie one input of a NAND gate permanently to VCC (Logic High), or one input of a NOR gate permanently to GND (Logic Low), forcing the gate to act as a single-input inverter.
