The standard ANSI/IEEE NOT gate symbol is a triangle pointing right with a small circle (bubble) on the output pin. In the IEC standard, it is a rectangle with a circle on the output and a '1' or 'NOT' inside. It performs logical inversion: a HIGH input yields a LOW output, and vice versa. Whether you are reading a legacy US military schematic or a modern European CAD export, recognizing these symbols and their physical IC equivalents is the first step in digital logic troubleshooting.
NOT Gate Symbol & Logic Variant Reference
While the basic inverter is straightforward, real-world schematics use modified NOT gate symbols to indicate specific electrical behaviors like hysteresis or open-drain outputs. Use this table to decode the exact variant on your schematic.
| Logic Variant | ANSI/IEEE Shape | IEC 60617 Shape | Practical Application & Bench Notes |
|---|---|---|---|
| Standard Inverter | Triangle + output bubble | Rectangle + output bubble + '1' inside | Basic logical negation. Use for clean digital signals where noise margins are guaranteed. |
| Schmitt Trigger Inverter | Triangle + output bubble + hysteresis loop inside | Rectangle + output bubble + hysteresis loop inside | Squaring noisy waveforms, switch debouncing, and RC oscillator building. Has distinct upper/lower voltage thresholds. |
| Open-Drain/Collector Inverter | Triangle + output bubble + diamond/line at bottom | Rectangle + output bubble + right-angle line at bottom | Wire-OR logic, I2C bus pulling, and driving loads higher than the logic Vcc. Requires an external pull-up resistor. |
| Buffer (Non-Inverting) | Triangle only (no bubble) | Rectangle only (no bubble) + '1' inside | Not a NOT gate, but often confused. Used for signal isolation, increasing fan-out, and driving heavy capacitive loads. |
| Inverter with Active-Low Input | Triangle + input bubble + output bubble | Rectangle + input bubble + output bubble | Electrically acts as a buffer. Used in De Morgan's equivalent schematics to maintain consistent active-low logic flow. |
Standard Hex Inverter IC Pinouts & Electrical Specs
Schematics show the logic; the silicon does the work. The most common physical embodiment of the NOT gate is the hex inverter (six independent NOT gates in one package). Below are the exact specifications for the three most common bench-stock hex inverters. Note that pinouts for Vcc and GND shift between the 74xx and 40xx series.
| IC Part Number | Logic Family | Vcc Range | Propagation Delay (tpd) | Max IOL (Sink) | Pinout (Vcc / GND) |
|---|---|---|---|---|---|
| 74HC04 | High-Speed CMOS | 2.0V - 6.0V | ~14 ns @ 5V | 4 mA | Pin 14 (Vcc) / Pin 7 (GND) |
| 74LS04 | Low-Power Schottky TTL | 4.75V - 5.25V | ~9 ns @ 5V | 8 mA | Pin 14 (Vcc) / Pin 7 (GND) |
| CD4049B | Standard CMOS Buffer | 3.0V - 15.0V | ~30 ns @ 5V | 16 mA (High Drive) | Pin 1 (Vdd) / Pin 8 (Vss) |
| SN74LVC1G04 | Low-Voltage CMOS (Single) | 1.65V - 5.5V | ~4 ns @ 3.3V | 32 mA | Pin 5 (Vcc) / Pin 2 (GND) [SOT-23-5] |
For detailed timing diagrams and DC characteristics, always cross-reference the Texas Instruments SN74HC04 datasheet or the equivalent manufacturer spec sheet for your specific logic family.
Regional Standards and Faded PCB Interpretation
The symbol you see on the page depends heavily on where and when the schematic was drawn.
ANSI/IEEE vs. IEC Standards
- ANSI/IEEE 91-1984: The 'distinctive shape' standard (triangles, D-shapes for AND gates). This is the default in US/Canadian university programs, legacy military documentation, and older textbooks like All About Circuits. It is highly intuitive for discrete gate visualization.
- IEC 60617-12: The 'rectangular' standard. Mandated in Europe and used by most modern international CAD tools (Altium, KiCad) for complex programmable logic. It scales better for massive FPGAs but is less visually distinct for beginners.
Interpreting Faded or Sanded IC Markings
If you are reverse-engineering a salvaged PCB and the hex inverter's top silkscreen is sanded off or faded, you can identify the chip and its logic family without desoldering it:
- Find Power and Ground: Use a multimeter in continuity mode. Probe Pin 7 and Pin 14. If Pin 14 is tied to the ground plane and Pin 7 to Vcc, it is likely a 4000-series CMOS (like the CD4049). If Pin 14 is Vcc and Pin 7 is ground, it is a 74-series IC.
- Identify the Family (TTL vs CMOS): Switch your multimeter to diode-test mode. Measure from an input pin (e.g., Pin 1) to the GND pin. Standard 74LS TTL has input clamping diodes to ground; you will read a ~0.6V drop. CMOS (74HC or CD40) will read 'OL' (open loop) in both directions.
- Verify Inversion and Hysteresis: Inject a 1kHz triangle wave from a function generator into an input pin. Monitor the output with an oscilloscope. If the output snaps to a clean, inverted square wave exactly at the 50% Vcc mark, it is a standard NOT gate (74HC04). If the output switches at distinct high and low thresholds (e.g., 65% on the rising edge, 35% on the falling edge), you are looking at a Schmitt Trigger inverter (74HC14).
Rows People Get Wrong: Bubble Placement and Active-Low Logic
When reading or drawing NOT gate equivalents, misinterpreting the 'bubble' (inversion circle) is the most common source of logic errors.
Mistake 1: The Input Bubble Means 'NOT'
A bubble on the input of a gate does not mean the gate itself is a NOT gate. It indicates an active-low input. For example, a NAND gate with a bubble on one input means that specific input is triggered when pulled LOW. If you see a triangle with a bubble on the input and a bubble on the output, the two inversions cancel out. Electrically, this is a non-inverting buffer, drawn this way to satisfy De Morgan's laws and keep active-low signal paths visually consistent.
Mistake 2: Ignoring the Schmitt Trigger Loop
Designers often omit the hysteresis loop inside the NOT gate symbol to save space, drawing a standard 74HC04 symbol when the BOM actually calls for a 74HC14 Schmitt trigger. If your circuit is experiencing high-frequency oscillation on a slow-rising input signal (like a capacitor charging curve or a mechanical switch), check the physical IC. Swapping a standard NOT gate for a Schmitt trigger NOT gate will instantly cure the chatter due to the built-in voltage hysteresis.
Mistake 3: Assuming Symmetrical Drive Strength
Beginners often assume a NOT gate can source as much current as it can sink. In standard CMOS (like the 74HC04), the P-channel MOSFET (pull-up) and N-channel MOSFET (pull-down) are roughly symmetrical, providing ~4mA in both directions. However, in older TTL families or specialized high-drive buffers like the NXP CD4049B, the sink current (IOL) is significantly higher than the source current (IOH). Always design your LED or relay driver circuits to pull current through the load to ground (active-low driving) rather than sourcing from the gate to Vcc.
Rule of Thumb: If you need to drive a load that requires more than 4mA, do not rely on a standard 74HC04 NOT gate. Use an open-drain inverter with a heavy-duty pull-up, or buffer the NOT gate output with a dedicated logic-level MOSFET like the 2N7000.
