The NOR2 symbol represents a 2-input NOR logic gate, which outputs a HIGH (1) only when both inputs are LOW (0). In practical bench and PCB work, this function is most commonly realized using a 14-pin DIP IC, specifically the 74HC02 (CMOS) or 74LS02 (TTL). Below is the complete reference data you need to read schematics, wire the IC correctly, and select the right part for your next build.
NOR2 Symbol Standards: ANSI, IEC, and DIN
Logic symbols vary depending on the drafting standard used in your region or by your EDA software. The IEEE 91-1984 standard (ANSI/IEEE) is dominant in the US, while IEC 60617 is standard in Europe and global industrial schematics. Here is how to read the NOR2 symbol across all three major conventions.
| Standard | Visual Shape | Internal Marking | Negation Indicator | Where You Will See It |
|---|---|---|---|---|
| ANSI/IEEE (Std 91) | D-shape with a curved back (like an OR gate) | None | Bubble (circle) on the output pin | US schematics, TI datasheets, hobbyist tutorials |
| IEC 60617 | Rectangular box | "≥1" (meaning OR logic) | Bubble on the output pin, or a bar over the output label | EU industrial prints, PLC ladder logic, global EDA tools |
| DIN 40700 (Obsolete) | Semi-circle with a flat vertical back | None | Bubble on the output pin | Vintage European manuals (pre-1990s), legacy military gear |
14-Pin DIP Pinout and Logic Truth Table
The physical pinout of the 74xx02 and CD4001 series is a notorious trap for hobbyists. Unlike the standard 7400 (NAND) or 7408 (AND) chips where inputs are on pins 1/2 and the output is on pin 3, the 7402 series reverses the input and output pins. Pin 1 is the output, and pins 2/3 are the inputs.
Standard 14-Pin DIP Mapping (74HC02 / CD4001)
| Pin | Function | Gate | Pin | Function | Gate |
|---|---|---|---|---|---|
| 1 | Y1 (Output) | Gate 1 | 8 | A3 (Input) | Gate 3 |
| 2 | A1 (Input) | Gate 1 | 9 | B3 (Input) | Gate 3 |
| 3 | B1 (Input) | Gate 1 | 10 | Y3 (Output) | Gate 3 |
| 4 | Y2 (Output) | Gate 2 | 11 | A4 (Input) | Gate 4 |
| 5 | A2 (Input) | Gate 2 | 12 | B4 (Input) | Gate 4 |
| 6 | B2 (Input) | Gate 2 | 13 | Y4 (Output) | Gate 4 |
| 7 | GND | Power | 14 | VCC | Power |
NOR2 Truth Table
| Input A | Input B | Output Y | Logic State Description |
|---|---|---|---|
| 0 (LOW) | 0 (LOW) | 1 (HIGH) | Only state that yields a HIGH output |
| 0 (LOW) | 1 (HIGH) | 0 (LOW) | Any HIGH input forces output LOW |
| 1 (HIGH) | 0 (LOW) | 0 (LOW) | Any HIGH input forces output LOW |
| 1 (HIGH) | 1 (HIGH) | 0 (LOW) | Both HIGH yields LOW |
Rows and Symbols People Get Wrong
When debugging a board or reading a complex schematic, misinterpreting a single row or symbol variant can lead to hours of wasted time. Here are the specific rows and visual cues that cause the most failures on the bench.
- The Pin 1 Row Trap: As noted in the pinout table, Pin 1 is Y1 (Output). If you wire Pin 1 as an input (assuming it matches a 7408 AND gate) and drive it HIGH while the chip internally drives it LOW, you create a direct short through the output transistor. This will overheat and destroy the silicon in seconds. Always verify the datasheet for the x02 series.
- The (0,0) Truth Table Row: Beginners often confuse NOR with NAND. A NAND gate outputs HIGH for three out of four states. A NOR gate outputs HIGH for only one state (0,0). If your logic probe shows a HIGH output when both inputs are floating or tied to ground, the chip is functioning correctly.
- IEC Bubble vs. Internal Bar: In some European PLC schematics, the IEC rectangle will show "≥1" but omit the output bubble, instead placing a small horizontal bar over the output letter (e.g., Q). This means the exact same thing as a bubble: active-low output. Do not wire it as a standard OR gate.
- Active-Low Input Bubbles: If you see an ANSI D-shape NOR2 symbol with bubbles on the inputs as well as the output, this is logically equivalent to an AND gate (De Morgan's Law). Schematics use this to indicate that the upstream signals are active-low. The physical chip is still a standard NOR2, but the logical intent is different.
Safe Interpretation When Markings Are Faded or Missing
When scavenging parts or repairing legacy PCBs where the silkscreen is burned off or the IC laser etching is unreadable, you must safely verify the gate type before integrating it into a live circuit. Never rely on visual guessing.
Bench Verification Procedure:
- Identify Power Pins: Assume standard 14-pin DIP layout. Connect Pin 14 to VCC (5V for 74HC, up to 15V for CD4000 series) and Pin 7 to GND. Place a 100nF decoupling capacitor across pins 7 and 14.
- Isolate Gate 1: Tie Pin 2 (A1) and Pin 3 (B1) to GND using 10kΩ pull-down resistors to prevent floating inputs, which cause erratic CMOS oscillation and excess current draw.
- Measure Output: Use a multimeter in DC voltage mode. Probe Pin 1. If it reads near VCC (e.g., 4.9V), you have a NOR (or NAND, proceed to next step). If it reads near 0V, it is likely an AND or OR gate.
- Force a HIGH Input: Disconnect Pin 2 from GND and tie it to VCC (Logic 1). Keep Pin 3 at GND (Logic 0). Probe Pin 1 again. If the voltage drops to ~0V, you have confirmed a NOR2 gate. (A NAND gate would still output HIGH in this state).
Decision Path: Which NOR2 IC to Buy
When sourcing a quad 2-input NOR gate for a new design or repair, your choice depends entirely on the voltage domain and speed requirements of your system. Use the decision matrix below to select the exact part number.
| System Condition / Requirement | Recommended IC Family | Exact Part Number (PDIP-14) | Why This Pick Wins |
|---|---|---|---|
| Standard 3.3V or 5V logic, Arduino/ESP32 interfacing, general DIY | 74HC (High-Speed CMOS) | SN74HC02N | Wide 2V-6V operating range, low power, high noise immunity. The modern default. |
| 12V automotive, 9V battery systems, analog synthesizer logic | 4000 Series CMOS | CD4001BE | Operates from 3V up to 18V. Slower switching, but handles high-voltage domains natively. |
| Repairing 1980s vintage computers, legacy 5V TTL backplanes | 74LS (Low-Power Schottky) | SN74LS02N | Exact electrical match for legacy TTL threshold voltages and bipolar current sinking. |
| High-frequency RF mixing, >50MHz clock distribution | 74LVC / 74AUC | SN74LVC02A | Nanosecond propagation delays, 3.3V optimized. (Note: Usually only available in SMD/SOIC, not DIP). |
The Default Pick: For 95% of hobbyist, student, and general-purpose bench applications, buy the Texas Instruments SN74HC02N. It is cheap, widely available in through-hole DIP-14 packages, and interfaces safely with both 5V Arduino and 3.3V ESP32 GPIO pins without needing level shifters, provided you respect the CD4001B style input voltage limits relative to VCC.
