A NOR gate outputs a logical HIGH only when all of its inputs are LOW. Because it is a universal gate, you can construct any other Boolean logic function (AND, OR, NOT, NAND) using only NOR gates. For modern 5V or 3.3V breadboard prototyping, the TI SN74HC02N quad 2-input NOR IC is the definitive default pick. However, before you drop an IC into your circuit, building a discrete Resistor-Transistor Logic (RTL) NOR gate with standard 2N3904 BJTs is the best way to internalize the underlying physics, loading effects, and failure modes that datasheets often obscure.

The 2-Input RTL NOR Gate Topology: Node Labels and Behavior

The discrete RTL NOR gate relies on two NPN bipolar junction transistors wired in parallel. When either transistor turns on, it creates a low-resistance path to ground, pulling the shared output node LOW.

Node Labels and Connections

  • Node A & Node B: Logic inputs (0V or 5V).
  • Node VCC: 5V DC supply.
  • Node GND: Common ground (0V).
  • Node Y (Output): The tied collectors of Q1 and Q2, pulled up to VCC via a resistor.
Bench Tip: In RTL, the transistors act as switchable current sinks. The pull-up resistor is what actually sources the HIGH voltage to the next stage when both transistors are OFF.

Behavior Table: Logic States

Input AInput BQ1 StateQ2 StateNode Y (Output)Logic Level
LOW (0V)LOW (0V)OFFOFF~5.0V (via Pull-up)HIGH (1)
HIGH (5V)LOW (0V)ON (Sat)OFF~0.2V (Vce_sat)LOW (0)
LOW (0V)HIGH (5V)OFFON (Sat)~0.2V (Vce_sat)LOW (0)
HIGH (5V)HIGH (5V)ON (Sat)ON (Sat)~0.2V (Vce_sat)LOW (0)

Design Walkthrough: Sizing the Resistors for a 5V RTL NOR

Let's design a discrete NOR gate to drive a standard logic probe or a high-impedance CMOS input. We will use onsemi 2N3904 NPN transistors, assuming a 5V VCC.

1. Sizing the Collector Pull-Up Resistor (Rc)

We need to limit the current when the transistors saturate (pull Node Y to GND) while keeping the RC time constant low enough for decent switching speed. Let's target a collector current (Ic) of 5mA when the output is LOW.

  • VCC = 5V
  • Vce(sat) = 0.2V (typical for 2N3904 at low currents)
  • Rc = (VCC - Vce(sat)) / Ic = (5V - 0.2V) / 0.005A = 960Ω

Concrete Pick: Use a standard 1kΩ resistor. This yields an actual Ic of 4.8mA.

2. Sizing the Base Resistors (Rb1, Rb2)

To guarantee the transistor acts as a hard switch (deep saturation), we must overdrive the base. The 2N3904 has a typical DC current gain (hFE or Beta) of ~100 at 5mA.

  • Minimum Ib required = Ic / hFE = 4.8mA / 100 = 48µA.
  • Overdrive factor = 10x (to ensure Vce stays below 0.2V despite temperature shifts or beta droop).
  • Target Ib = 480µA.
  • Vbe(sat) = 0.7V.
  • Rb = (VCC - Vbe) / Target Ib = (5V - 0.7V) / 0.00048A = 8,958Ω.

Concrete Pick: Use standard 10kΩ resistors for Rb1 and Rb2. This provides 430µA of base current, yielding a forced beta of ~11, which easily saturates the 2N3904.

Failure Mode Contrast: What Breaks at the Extremes?

Understanding how a circuit fails is just as critical as knowing how it works. Here is what happens when components fail open or short in this parallel RTL topology.

Hazard Alert: Never short the base resistors (Rb1/Rb2) on a breadboard if your input signal is sourced from a low-impedance 5V supply.
Failure ModeCircuit BehaviorPhysical Consequence
Short Rb1Input A connects directly to Q1 Base.If A goes HIGH (5V), the base-emitter junction acts as a diode to GND. Massive current flows, exceeding the 50mA max base rating, permanently popping the B-E junction open.
Open Q1 CollectorThe parallel pull-down path for Q1 is broken.The circuit degrades into a single-input inverter. Node Y will only go LOW when Input B is HIGH; Input A is entirely ignored.
Short Q1 C-ENode Y is physically tied to GND through the transistor.Output is stuck permanently LOW (~0.2V) regardless of inputs. Rc dissipates continuous power (25mW), which is safe for a 1/4W resistor but wastes current.
Open Rc (Pull-up)Node Y loses its path to VCC.Output floats. It will read LOW when a transistor is ON, but will float to an undefined voltage (or read 0V on a multimeter due to input impedance) when both are OFF.

Breadboard Verification: Step-by-Step Testing Protocol

Follow this sequence to verify your discrete RTL NOR gate without risking your test equipment or components.

  1. De-energize and Prep: Ensure the breadboard power supply is OFF. Insert two 2N3904 transistors, leaving at least two empty rows between them to prevent accidental bridging.
  2. Wire the Emitters: Connect both emitters (pin 1, assuming flat-side facing you and pins are E-B-C left-to-right) directly to the GND rail.
  3. Install Base Resistors: Insert the 10kΩ resistors (Rb1, Rb2). Connect one end to the respective bases, and leave the other ends free for your logic inputs (Node A and Node B).
  4. Tie Collectors and Pull-Up: Jumper the collectors together (Node Y). Insert the 1kΩ resistor (Rc) between Node Y and the 5V VCC rail.
  5. Quiescent Check: Turn ON the 5V supply. Leave Inputs A and B unconnected (floating LOW). Measure Node Y with a DMM. It should read ~4.9V to 5.0V.
  6. Inject Logic HIGH: Use a jumper wire to momentarily connect Node A to the 5V rail. Node Y should immediately drop to < 0.3V. Remove the jumper; Node Y should return to 5V.
  7. Verify the 'Both HIGH' State: Jumper both Node A and Node B to 5V simultaneously. Node Y must remain LOW. If it rises, one of your transistors is failing to saturate (check your Rb connections).

Decision Matrix: Discrete RTL vs. 74HC02 vs. CD4001

While building an RTL gate is an excellent learning exercise, it is rarely the right choice for a finished product or complex logic array. Here is how the discrete topology stacks up against standard integrated CMOS logic.

CriteriaDiscrete RTL (2N3904)74HC02 (CMOS)CD4001 (CMOS)
Propagation Delay~100ns - 500ns (depends on load C)~14ns (at 5V)~60ns (at 5V)
Current Drive (5V)~5mA (sink only, source via Rc)±25mA (symmetrical)±4.2mA (symmetrical)
Fan-OutLow (2-3 TTL loads)High (15+ LSTTL loads)Low (1 LSTTL load)
Operating VoltageDepends on VCC and B-E breakdown2.0V to 6.0V3.0V to 15.0V
Component Count5 parts per gate1 IC contains 4 gates1 IC contains 4 gates

Why the 74HC02 Wins for Modern Logic Prototyping

When designing a NOR logic gate circuit for a real-world application, you need a decision path that terminates in a concrete part number. Use this framework to make your pick:

  • If your goal is purely educational (learning BJT saturation, forced beta, and discrete failure modes) → Build the Discrete RTL circuit detailed above.
  • If you are interfacing with 12V automotive systems or need to operate from an unregulated 9V battery → Choose the CD4001BE. Its 15V maximum VCC tolerance handles noisy, high-voltage environments that would fry a 74-series chip.
  • If you are building standard 3.3V or 5V digital logic, driving LEDs, or interfacing with microcontrollers (Arduino/ESP32) → Choose the 74HC02.
The Default Pick: For 95% of bench prototyping and DIY logic circuits, buy the TI SN74HC02N. It offers symmetrical 25mA drive capability (enough to light a standard 20mA LED directly without a buffer transistor), rail-to-rail CMOS output swings, and a propagation delay fast enough to handle SPI/I2C edge rates without signal degradation. Furthermore, as documented in the All About Circuits RTL guide, moving from discrete RTL to integrated CMOS eliminates the static power draw that occurs when RTL transistors are saturated, dropping your quiescent current from milliamps down to microamps.

By understanding the discrete RTL topology, you now know exactly what is happening inside the silicon of that 74HC02 IC. You understand why the pull-up network matters, why saturation voltage dictates your LOW threshold, and exactly what happens when a node shorts to ground. Grab your DMM, wire up the 2N3904s, and verify the physics on your bench before you commit to the IC.