An NMOS current mirror is a fundamental integrated circuit building block that uses matched NMOS transistors to copy a reference current into one or more output branches. In real silicon design, it changes everything: it replaces area-hungry, temperature-drifting physical resistors with compact, precise active current sources that scale predictably across a die, enabling high-gain amplifiers and stable biasing networks that would be impossible with passive components.

To understand the core mechanism, think of a water system where a pressure regulator valve (the diode-connected reference transistor) opens just enough to pass a specific reference flow. A second, physically identical valve downstream (the mirroring transistor) is linked to the exact same control pressure (the gate-source voltage, $V_{GS}$). Because they share the same gate 'pressure', they pass the same flow, provided the downstream drain pressure is high enough to keep both valves fully operational (in saturation).

The Core Mechanism and Sizing Math

A basic NMOS current mirror consists of two transistors. M1 is 'diode-connected' (gate shorted to drain), forcing it into saturation and establishing a gate-source voltage ($V_{GS}$) dictated by the reference current ($I_{REF}$). M2 shares this $V_{GS}$. If M1 and M2 are perfectly matched and experience the same drain-source voltage ($V_{DS}$), their drain currents are identical.

However, in real analog design, we must account for channel-length modulation (the Early effect in BJTs), where current increases slightly with $V_{DS}$. The governing equation for an NMOS transistor in saturation is:

I_D = 0.5 * μ_n * C_ox * (W/L) * (V_GS - V_TH)^2 * (1 + λ * V_DS)

Design Assumption Note: The following numeric example assumes a standard 180nm CMOS process at 300K, with electron mobility times oxide capacitance ($μ_nC_{ox}$) = 200 μA/V², threshold voltage ($V_{TH}$) = 0.4V, and channel-length modulation parameter ($λ$) = 0.05 V⁻¹.

Worked Numeric Example: Sizing for 100 μA

Suppose you need to design a basic NMOS mirror to generate an output current $I_{OUT} = 100 \mu A$. You set $I_{REF} = 100 \mu A$ and choose a gate-source voltage $V_{GS} = 0.65V$ to ensure a healthy overdrive voltage ($V_{OV} = V_{GS} - V_{TH} = 0.25V$) for good speed and noise performance.

  1. Identify M1 parameters: Because M1 is diode-connected, $V_{DS1} = V_{GS1} = 0.65V$.
  2. Plug into the saturation equation:
    $100\mu A = 0.5 \times 200\mu A/V^2 \times (W/L) \times (0.65V - 0.4V)^2 \times (1 + 0.05 \times 0.65V)$
  3. Simplify the terms:
    $100 = 100 \times (W/L) \times (0.25)^2 \times (1 + 0.0325)$
    $100 = 100 \times (W/L) \times 0.0625 \times 1.0325$
    $100 = 6.453 \times (W/L)$
  4. Solve for W/L:
    $W/L = 100 / 6.453 \approx 15.5$

To minimize the impact of channel-length modulation ($λ$) and improve matching, analog designers rarely use the minimum channel length (0.18 μm here). We select $L = 1 \mu m$, which dictates $W = 15.5 \mu m$. If $I_{OUT}$ needs to be scaled to $300 \mu A$, we simply triple the width of M2 to $46.5 \mu m$ while keeping $L = 1 \mu m$.

Topology Comparison: Basic vs. Cascode vs. Wilson

The basic 2-transistor mirror suffers from low output impedance due to channel-length modulation. If the voltage at the drain of M2 changes, $I_{OUT}$ drifts. To fix this, IC designers use advanced topologies. The table below breaks down the four most common NMOS mirror architectures you will encounter in MIT's microelectronic device coursework and professional silicon design.

Topology Output Impedance ($R_{out}$) Min Output Voltage ($V_{OUT(min)}$) Headroom Penalty Best Application
Basic 2-Transistor $r_o$ (Low) $V_{OV}$ Low Non-critical biasing, low-voltage IoT sensors
Standard Cascode $g_m r_o^2$ (Very High) $V_{OV} + V_{TH}$ High High-gain op-amp active loads, precision DACs
Low-Voltage (Wide-Swing) Cascode $g_m r_o^2$ (Very High) $2V_{OV}$ Low Modern deep-submicron (FinFET) low-voltage analog blocks
Wilson Current Mirror $g_m r_o^2$ (Very High) $V_{OV} + V_{TH}$ High High-frequency RF biasing (avoids cascode Miller capacitance)

Notice the trade-off: achieving high output impedance ($g_m r_o^2$) requires stacking transistors, which eats into your voltage headroom. In a 1.2V supply, a standard cascode might leave insufficient room for the signal swing, making the wide-swing cascode mandatory.

Where You Meet This in Practice

You will rarely build an NMOS current mirror on a breadboard with discrete MOSFETs (like the CD4007) because discrete devices lack the strict thermal and geometric matching required for accuracy. This circuit lives almost entirely inside integrated circuits. Here is where it does the heavy lifting:

  • Differential Pair Tail Currents: In every operational amplifier, an NMOS current mirror acts as the 'tail' current source for the input differential pair. It provides a high-impedance path to ground, directly dictating the Common-Mode Rejection Ratio (CMRR). A poorly designed mirror here limits CMRR to < 50dB, whereas a cascode mirror pushes it > 80dB.
  • Active Loads: Instead of using resistors to pull up the drains of an NMOS differential pair (which wastes voltage headroom and limits gain), designers use a PMOS current mirror as an active load. The PMOS mirror converts the differential signal to single-ended while providing massive small-signal resistance.
  • Bandgap Reference Biasing: The core of a temperature-stable voltage reference relies on forcing identical currents through two bipolar transistors operating at different current densities. NMOS current mirrors guarantee those currents remain perfectly matched across the -40°C to 125°C industrial temperature range.

Common Pitfalls and Confusions

Layout is Everything: In silicon, drawing two identical rectangles for M1 and M2 is not enough. Process gradients across the die will cause mismatch. Designers must use interdigitated layouts (e.g., M1-M2-M2-M1 finger patterns) and surround the array with dummy devices to ensure identical etching and stress environments. See the All About Circuits semiconductor guide for deeper layout theory.

What do people commonly confuse it with?

The most frequent confusion occurs between NMOS mirrors and BJT (Bipolar) current mirrors. In a BJT mirror, base current steals from the reference current, causing a systematic error proportional to $1/\beta$. Designers must add a third transistor (a beta-helper) to fix this. In an NMOS mirror, the gate draws virtually zero DC current (only sub-nanoamp leakage). Therefore, the basic 2-transistor NMOS mirror has no DC transfer ratio error from gate current; its primary error source is strictly $V_{DS}$ mismatch causing channel-length modulation.

Another common trap is confusing the minimum compliance voltage of the basic mirror with the cascode. A junior designer might use a basic mirror in a low-voltage design, only to realize that while the basic mirror allows the output to swing down to $V_{OV}$ (e.g., 0.2V), the output transistor enters the triode (linear) region just below that, destroying the output impedance and collapsing the gain of the amplifier stage.

Troubleshooting a Failing Mirror in Simulation

If your SPICE simulation shows $I_{OUT}$ drifting significantly from $I_{REF}$:

  1. Check $V_{DS}$ matching: Plot $V_{DS1}$ and $V_{DS2}$. If they differ by more than a few millivolts, channel-length modulation is skewing your ratio. Switch to a cascode topology.
  2. Verify Saturation: Ensure $V_{DS2} > V_{GS2} - V_{TH}$. If the output node is pulled too low by the subsequent stage, M2 enters the triode region and acts like a resistor, not a current source.
  3. Inspect Transient Gate Ringing: The gate of a current mirror is a high-impedance node with significant parasitic capacitance. If your reference current has high-frequency noise, it will couple through the gate capacitance and modulate the output. Add a small decoupling capacitor from the shared gate node to ground if bandwidth permits.