Designing an NMOS Common Source Amplifier: Biasing, Gain, and Pitfalls

An NMOS common source amplifier is a fundamental transistor circuit configuration where the source terminal is tied to ground, the input signal drives the gate, and the amplified, phase-inverted output is extracted from the drain. In a real circuit, this topology changes the game by acting as a high-impedance voltage-controlled voltage source; it translates millivolt-level sensor or audio signals into usable volt-rail swings without drawing current from (and thus loading down) the preceding high-impedance stage. Whether you are building an RF front-end or interfacing a piezo sensor to a microcontroller, this circuit is the workhorse of analog design. However, getting the DC bias point right—and avoiding the trap of assuming textbook parameters match silicon reality—is where most hobbyists and students hit a wall.

The Core Mechanism: How the NMOS Common Source Amplifier Works

The physics of the NMOS common source amplifier relies on the electric field effect. When you apply a positive voltage to the gate relative to the source ($V_{GS}$), it creates an inversion layer (a conductive channel) between the drain and source. Once $V_{GS}$ exceeds the threshold voltage ($V_{th}$), current ($I_D$) begins to flow.

For amplification, we must operate the MOSFET in the saturation region (also called the active region in some textbooks), where the drain current is largely independent of the drain-source voltage ($V_{DS}$) and is controlled almost entirely by the gate voltage. The governing equation for DC drain current in saturation is:

$$I_D = \frac{1}{2} k_n (V_{GS} - V_{th})^2$$

When a small AC signal ($v_{gs}$) is superimposed on the DC gate bias, it causes small fluctuations in the drain current. This fluctuating current passes through a drain resistor ($R_D$), creating a fluctuating voltage drop. Because the output voltage is measured at the drain relative to the supply rail ($V_{DD}$), an increase in gate voltage causes an increase in current, which drops more voltage across $R_D$, thereby lowering the output voltage. This results in a 180-degree phase inversion.

Worked Numeric Example: Biasing a 2N7000 for Maximum Swing

Let us design a discrete amplifier using the ubiquitous ON Semiconductor 2N7000 NMOS transistor. Our goal is maximum symmetrical output voltage swing, which requires biasing the drain voltage ($V_{DS}$) at exactly half the supply rail.

Step 1: Calculate the Drain Resistor ($R_D$)
To drop 6V at 2mA, Ohm's law gives us:
$R_D = (V_{DD} - V_{DS}) / I_D = (12V - 6V) / 2mA = 3,000\Omega$.
Practical note: We would use a standard 1% 3.01kΩ resistor on the bench.

Step 2: Calculate Required Gate Bias ($V_{GS}$)
Rearranging the saturation current equation to solve for $V_{GS}$:
$2mA = 0.5 \times 20 mA/V^2 \times (V_{GS} - 2.0V)^2$
$0.2 = (V_{GS} - 2.0)^2$
$V_{GS} - 2.0 = \sqrt{0.2} \approx 0.447V$
$V_{GS} = 2.45V$

Step 3: Calculate Transconductance ($g_m$) and Voltage Gain ($A_v$)
The small-signal transconductance is:
$g_m = \sqrt{2 \times k_n \times I_D} = \sqrt{2 \times 20 \times 2} = \sqrt{80} \approx 8.94 mA/V$
The theoretical voltage gain (assuming no external load) is:
$A_v = -g_m \times R_D = -8.94 mA/V \times 3k\Omega = -26.8 V/V$

The Real-World Catch: If you build this exact circuit using a fixed 2.45V voltage divider on the gate, it will likely fail. Why? Because the $V_{th}$ of a 2N7000 can vary from 0.8V to 3.0V between individual parts. A fixed $V_{GS}$ bias will push some transistors into cutoff and others into the triode (linear) region. In practice, we add a source degeneration resistor ($R_S$) with a bypass capacitor to stabilize the DC bias point against manufacturing spreads and temperature drift (Electronics Tutorials covers this stabilization in depth).

Where You Meet This in Practice (and What It Changes)

You will encounter the NMOS common source amplifier in several critical domains:

• RF Front-Ends: Low Noise Amplifiers (LNAs) in software-defined radios (SDRs) often use common source topologies with inductive loads to maximize gain while minimizing thermal noise.
• Sensor Signal Conditioning: High-impedance sensors like piezoelectric film or electret microphones require an amplifier that draws virtually zero DC gate current. The NMOS common source provides this massive input impedance advantage over bipolar junction transistors (BJTs).
• Op-Amp Internal Stages: If you look at the internal schematic of a CMOS operational amplifier like the TLC27M2, the input differential pair is essentially two common source amplifiers operating in parallel.

What people most commonly confuse this with is the Common Drain (or Source Follower) configuration. In a source follower, the output is taken from the source terminal, yielding a voltage gain of slightly less than 1, no phase inversion, and a low output impedance. While the common source is used for voltage amplification, the common drain is used for current buffering and impedance matching.

Real-World Scenario Walkthrough: The Piezo Preamp Clipping Disaster

Let us look at a scenario that has burned many a bench hour. A maker is building a knock-sensor alarm using a piezo disc and an ESP32. They need to amplify the piezo signal to hit the 3.3V ADC range.

The Setup:
They wire a BS170 NMOS in a common source configuration. $V_{DD}$ is 3.3V. They use a 10kΩ drain resistor and set a voltage divider to bias the gate at 1.8V. They connect the piezo directly to the gate via a 100nF coupling capacitor.

The Numbers:
A sharp tap on the piezo disc generates an open-circuit voltage spike of up to 40V. The ESP32 ADC is sampling at 10kHz.

The Outcome:
The ESP32 serial plotter shows a flat 3.3V line, occasionally dropping to 0V. The MOSFET is hot to the touch, and the expected acoustic ringing waveform is completely absent, replaced by a harsh square wave.

What Went Wrong:
Two critical errors occurred here. First, piezo elements are essentially capacitors; without a high-value pulldown resistor on the gate, the coupling capacitor charges up and shifts the DC bias point entirely out of the saturation region. Second, the 40V transient spike massively exceeded the gate-source breakdown voltage ($V_{GS(max)}$ is typically ±20V for small-signal MOSFETs). The gate oxide experienced punch-through, permanently damaging the silicon and leaving the transistor partially shorted.

Common Confusions: Common Source vs. Common Drain vs. BJT

To ensure you are selecting the right topology for your schematic, compare these three fundamental amplifier stages:

For a deeper dive into the mathematical derivations of these small-signal models, the All About Circuits semiconductor textbook provides excellent chapter-by-chapter breakdowns of FET behavior compared to bipolar junction transistors.

Frequently Asked Questions