The NMOS (N-channel Metal-Oxide-Semiconductor) circuit symbol tells you exactly how the device switches current from Drain to Source when a positive voltage hits the Gate. Whether you are reading a datasheet, designing a PCB in KiCad, or troubleshooting a blown H-bridge, misinterpreting this symbol leads to dead silicon. Below is the direct reference for identifying, drawing, and testing NMOS transistors across global standards.
The NMOS Circuit Symbol Reference Table
Schematics vary based on the drafting standard and the specific physics of the transistor. Use this table to identify exactly what you are looking at on a schematic.
| Symbol Variant | Standard | Visual Key | Practical Circuit Meaning |
|---|---|---|---|
| Enhancement NMOS (3-pin) | IEEE 315 (US) | Vertical channel line, 3 horizontal lines (G, D, S). Arrow on Source points IN toward channel. Gate line is broken (insulated). | Default for 95% of power and logic switching. Device is normally OFF. Requires positive Vgs to turn ON. |
| Enhancement NMOS (4-pin) | IEEE 315 (US) | Same as above, but includes a 4th line for Bulk/Body (B) connected to the channel. | Used in IC design. In discrete parts, Bulk is internally tied to Source. Shows the substrate connection explicitly. |
| Enhancement NMOS (Box) | IEC 60617 (EU) | Rectangular box for the channel. Gate, Drain, Source lines extend from the box. No arrow; polarity indicated by 'N' or channel type marker. | Common in European industrial schematics and older military prints. Functionally identical to IEEE enhancement mode. |
| Depletion NMOS | IEEE 315 (US) | Vertical channel line is SOLID (unbroken) between Drain and Source. Arrow on Source points IN. | Normally ON device. Requires a negative Vgs to turn OFF. Used in RF amps and constant-current sources. |
| NMOS with Body Diode | IEEE 315 (US) | Enhancement symbol with a diode symbol drawn between Drain and Source (cathode at Drain, anode at Source). | Explicitly shows the intrinsic parasitic body diode. Crucial for motor drive and high-side switching schematics. |
Standard Variants: IEEE 315 vs. IEC 60617
Your region and your EDA (Electronic Design Automation) software defaults dictate which symbol you will encounter. Understanding the difference prevents cross-border collaboration errors.
IEEE 315 / ANSI Y32.2 (North America & Global Default): This is the 'line-and-arrow' style. The critical identifier for NMOS is the arrow on the Source pin pointing inward toward the channel line. (Remember: 'N' means 'Not pointing out' for the arrow, whereas PMOS arrows point out). The gap between the Gate line and the channel line represents the silicon dioxide insulating layer.
IEC 60617 (Europe & International Industrial): The IEC standard favors rectangular enclosure boxes rather than stylized junction lines. The NMOS is drawn as a box with a straight line through it representing the channel. Polarity is often denoted by a small 'N' inside the box or by the direction of a small arrow on the substrate line, rather than the prominent source arrow seen in IEEE. If you are using Altium Designer or KiCad, the default libraries almost exclusively use the IEEE 315 symbols, but imported European machinery schematics will use IEC.
Rows People Get Wrong (and How to Fix Them)
Misreading an NMOS symbol usually results in a short circuit or a non-functional board. Here are the most common schematic interpretation failures:
- Confusing NMOS with NPN BJT: Both have arrows pointing inward. However, the BJT arrow is on the Emitter and the base line connects directly to the vertical channel. The NMOS arrow is on the Source, and the Gate line is physically separated from the channel by a gap. If there is no gap, you are looking at a Bipolar Junction Transistor, which requires continuous base current to stay on.
- Ignoring the Implicit Body Diode: Most discrete power NMOS symbols (like the IRFZ44N) do not draw the body diode in the schematic symbol to save space. However, the physical silicon always has an intrinsic diode from Source to Drain. If you use an NMOS as a high-side switch without accounting for this, the diode will permanently conduct current to your load, bypassing your gate control entirely.
- The 4-Pin Bulk Trap: In IC schematics, you will see a 4-pin NMOS symbol where the Bulk (B) pin is tied to the lowest voltage in the circuit (usually GND). When translating this to a discrete 3-pin board layout, you must remember that the discrete part's bulk is internally hardwired to the Source pin. You cannot independently bias the bulk on a standard TO-220 or SOT-23 MOSFET.
Physical Pinout & Identifying Faded MOSFETs
Symbols on a screen are clean; physical parts on a bench are not. If the laser etching on your MOSFET is burned off, or you are dealing with unmarked salvage parts, you must safely interpret the physical pinout using a multimeter.
Safety First: Never test a MOSFET while it is soldered into a live circuit. Desolder at least the Gate and Drain, or remove the component entirely. Stray voltages will destroy the thin gate oxide layer and yield false multimeter readings.
Standard Pinouts (Looking at the front, text readable, pins pointing down):
- TO-220 (Through-hole power): Pin 1 = Gate, Pin 2 = Drain (also tied to the metal tab), Pin 3 = Source.
- SOT-23 (Surface mount logic): Pin 1 = Gate, Pin 2 = Source, Pin 3 = Drain. (Note the swap of Drain and Source compared to TO-220).
The Multimeter Diode Test (Safe Interpretation):
Set your multimeter to Diode Test mode. Because the NMOS body diode connects Source (Anode) to Drain (Cathode), you can identify the pins even on completely unmarked black epoxy packages.
- Place the Red probe on Pin A and the Black probe on Pin B.
- If you read a forward voltage drop between 0.40V and 0.65V, Pin A is the Source and Pin B is the Drain.
- Swap the probes. It should read 'OL' (Open Loop). If it reads near 0.00V in both directions, the MOSFET is shorted and dead.
- The remaining third pin is the Gate. To verify, touch the Red probe to the Gate and Black to the Source to charge the gate capacitance. Then measure Drain to Source again; it should now read near 0.00V (the channel is turned on). Short Gate to Source to discharge it, and it will return to 'OL'.
Decision Path: Which NMOS Symbol and Part to Pick
Stop guessing which MOSFET to drop into your schematic. Use this decision tree to select the correct symbol variant and terminate on a concrete, purchasable part number for your specific application.
| Application Scenario | Required Symbol Type | Critical Parameter | Concrete Part Pick (2026 Standard) |
|---|---|---|---|
| Switching low-side DC loads (motors, heaters, LED strips) from a 5V or 3.3V microcontroller GPIO. | Enhancement NMOS (IEEE 3-pin, body diode implied) | Logic-level Gate threshold (Vgs_th < 2.5V), Low Rds(on) at 4.5V. | IRLZ44N (TO-220) or IRLML6244 (SOT-23) |
| Level shifting, simple signal switching, or driving small relays from 5V logic. | Enhancement NMOS (IEEE 3-pin) | Low cost, low current (<300mA), standard Vgs_th. | 2N7000 (TO-92) or BSS138 (SOT-23) |
| High-voltage switching (100V+), solar charge controllers, or 48V battery bank management. | Enhancement NMOS (IEEE 3-pin, explicitly draw body diode) | High Vds rating (>100V), avalanche rated. | IRFB4227 (100V) or IXTH88N30P (300V) |
| RF amplification, constant current sources, or solid-state depletion loads. | Depletion NMOS (IEEE solid channel line) | Normally ON at Vgs=0V, turns off with negative Vgs. | LND150 or BSS126 |
Default Recommendation: If you are building a general-purpose DIY project, robotics chassis, or home automation node and need a low-side power switch, standardize your schematic library on the IEEE 3-pin Enhancement NMOS symbol and stock your bench with IRLZ44N transistors. They are logic-level, handle up to 47A continuous current with a heatsink, and survive the 5V GPIO outputs of an Arduino or ESP32 without requiring a dedicated gate driver IC.
