The standard NE555 timer pinout uses an 8-pin configuration where Pin 1 is Ground (GND), Pin 8 is VCC, and Pin 1 is always located immediately counter-clockwise from the orientation notch or molded dot. Whether you are wiring an astable multivibrator or a monostable one-shot, getting these eight connections right is the difference between a stable clock signal and a melted chip.
The Complete NE555 Timer Pinout Reference Table
Below is the definitive pinout for the bipolar NE555. This mapping applies universally across the standard 8-pin DIP (Dual In-line Package) and SOIC (Small Outline IC) footprints.
| Pin | Name | Function | Practical Notes & Thresholds |
|---|---|---|---|
| 1 | GND | Ground Reference | 0V reference. Must share a clean ground plane with your timing capacitor to prevent jitter. |
| 2 | TRIG | Trigger Input | Starts the timing cycle when voltage drops below 1/3 VCC. High impedance (>1MΩ). |
| 3 | OUT | Output | Push-pull stage. Can source or sink up to 200mA. High state is ~VCC - 1.5V. |
| 4 | RESET | Master Reset | Active LOW. Overrides TRIG. Must be tied to VCC if not used. Threshold is ~0.7V. |
| 5 | CTRL | Control Voltage | Accesses the internal 2/3 VCC voltage divider. Requires a 10nF to 100nF bypass cap to GND. |
| 6 | THR | Threshold Input | Stops the timing cycle when voltage exceeds 2/3 VCC. |
| 7 | DIS | Discharge | Open-collector NPN transistor. Sinks current to discharge the timing capacitor. Cannot source current. |
| 8 | VCC | Positive Supply | 4.5V to 16V nominal (18V absolute max). Draws ~10mA quiescent current. |
Package Standards, Variants, and Faded Markings
While the logical pinout remains identical, the physical packaging standards dictate how you read and solder the chip. Unlike mains wiring which varies by region (NEC vs. IEC), IC packaging follows global JEDEC standards.
DIP-8 vs. SOIC-8 vs. VSSOP-8
- DIP-8 (JEDEC MS-001): The classic 0.3-inch wide through-hole package (e.g., NE555P). Pin 1 is identified by a semicircular notch at the top and a small molded dot next to Pin 1.
- SOIC-8 (JEDEC MS-012): The standard surface-mount variant (e.g., NE555DR). The pinout mapping is identical, but the pitch is 1.27mm. Pin 1 is marked by a laser-etched dot or a beveled edge on the plastic body.
- VSSOP-8 / TSSOP-8: Ultra-compact SMD packages (e.g., NE555PW). The pinout wraps the same way, but the pitch shrinks to 0.65mm, requiring a stencil and reflow oven or precise hot-air work.
Bipolar vs. CMOS Variants
The original bipolar Texas Instruments NE555 shares its exact pinout with modern CMOS replacements like the TLC555, LMC555, and ICM7555. However, their internal architectures differ wildly. The bipolar NE555 draws ~10mA of quiescent current and generates a massive ~100mA supply current spike during output switching. CMOS variants draw under 1mA and eliminate the switching spike, but their output drive capability drops from 200mA to roughly 100mA.
Safe Interpretation of Faded or Missing Markings
When salvaging parts or dealing with counterfeit chips, laser etching is often sanded off. Never guess the orientation. If the top dot is missing, look for the beveled edge on the bottom-left corner of the DIP package. If the physical mold marks are entirely gone, you can use a multimeter in diode-test mode: measure between the suspected GND (Pin 1) and VCC (Pin 8). A reading of ~0.5V to 0.7V in one direction (and OL in the reverse) confirms the internal protection diode orientation, verifying your Pin 1 assumption.
Pins and Rows People Get Wrong
Even experienced makers trip over specific quirks of the 555 architecture. Here are the most common wiring failures and how to avoid them.
Row 1 (Pins 1-4): The Floating Reset Trap
Leaving Pin 4 (RESET) unconnected is a guaranteed way to ruin your circuit's stability. Because RESET is an active-LOW input with high impedance, stray electromagnetic noise on your breadboard will induce voltage dips below the 0.7V threshold, randomly resetting your timer. The Fix: Always tie Pin 4 directly to Pin 8 (VCC) if you are not using an external reset switch.
Row 2 (Pins 5-8): The Pin 7 vs. Pin 3 Confusion
Makers frequently try to drive an LED or a relay directly from Pin 7 (DIS), assuming it acts like the main output. Pin 7 is an open-collector NPN transistor. It can sink current to ground when the internal flip-flop is set, but it cannot source current from VCC. If you connect an LED between VCC and Pin 7 without a current-limiting resistor, you will fry the internal transistor when it turns on. The Fix: Use Pin 3 (OUT) for driving loads (it is a push-pull stage that can both source and sink 200mA). Use Pin 7 strictly for discharging timing capacitors or as a logic-level open-drain signal.
The Missing Pin 5 Bypass Capacitor
Pin 5 (CTRL) taps directly into the internal resistor ladder that sets the 2/3 VCC threshold. Without a bypass capacitor, this node acts as an antenna, picking up high-frequency noise that modulates your threshold voltage, resulting in severe timing jitter. The Fix: Solder a 10nF (0.01µF) to 100nF (0.1µF) ceramic capacitor directly between Pin 5 and Pin 1, keeping the leads as short as physically possible.
NE555 Timer Pinout FAQ
Can I use a CMOS 555 (TLC555) with the exact same NE555 timer pinout?
Yes, the pinout is 100% identical, and it will drop directly into the same PCB footprint. However, you must account for the lower output drive current of the CMOS version (typically 100mA vs. the bipolar's 200mA). If your circuit relies on the NE555 to directly drive a high-current relay coil or a bright incandescent lamp, the TLC555 will overheat. Add a 2N2222 or logic-level MOSFET to buffer the output when switching to CMOS.
What happens if I wire the NE555 timer pinout backward (VCC and GND swapped)?
The chip will die almost instantly. The NE555 contains internal parasitic substrate diodes. When you reverse the polarity, these diodes become forward-biased, creating a dead short across your power supply. The chip will draw massive current, overheat, and often physically crack or pop. Always verify Pin 1 and Pin 8 with a multimeter's continuity checker against your known ground plane before applying power.
How do I identify Pin 1 on an unmarked or heavily sanded NE555 chip?
If the top dot and the notch are gone, examine the edges of the DIP package under a magnifying glass. Manufacturers often leave a slight bevel or chamfer on the edge nearest to Pin 1. If the package is completely smooth, look at the bottom: the internal leadframe tie-bar (the metal strip connecting the pins during manufacturing) is sometimes snipped closer to Pin 1. If all physical indicators are destroyed, discard the IC; the risk of reverse-polarity destruction is not worth the $0.50 replacement cost.
