A standard 2-input NAND gate at the transistor level requires exactly four transistors in a Complementary MOS (CMOS) configuration: two PMOS transistors wired in parallel for the pull-up network, and two NMOS transistors wired in series for the pull-down network. While you can buy a quad-NAND IC for pennies, understanding the nand transistor level architecture is critical when you need to build discrete logic for high-voltage applications, troubleshoot a failing chip, or design custom silicon layouts.
Unlike older Bipolar Junction Transistor (BJT) logic like TTL, which relied on complex multi-emitter transistors and wasted milliamps of current as heat, CMOS logic draws virtually zero static current. Here is exactly how the silicon works, how to build it on your bench, and how to test it when things go wrong.
The CMOS NAND Transistor Level Schematic Explained
If you look at the internal schematic of a standard 14-pin DIP NAND IC (like the 74HC00), each of the four gates shares the same topology. Let us map the physical pins to the internal transistor symbol.
Pin 1 (1A): Input A. Connects to the gate of PMOS transistor Q1 and NMOS transistor Q3.
Pin 2 (1B): Input B. Connects to the gate of PMOS transistor Q2 and NMOS transistor Q4.
Pin 3 (1Y): Output Y. The junction where the PMOS sources (tied to VCC) meet the NMOS drain (tied to GND).
Pin 14 (VCC): Positive supply (tied to the source of Q1 and Q2).
Pin 7 (GND): Ground (tied to the source of Q4).
How it switches: NMOS transistors are excellent at pulling a line down to ground (passing a logic 0), while PMOS transistors are excellent at pulling a line up to VCC (passing a logic 1). When both inputs A and B are HIGH, both NMOS transistors (Q3 and Q4) turn on, creating a low-resistance path to ground. Simultaneously, both PMOS transistors turn off. The output is pulled LOW. If either input goes LOW, the series NMOS path is broken, but at least one parallel PMOS transistor turns on, pulling the output HIGH. This yields the exact inverse of an AND gate.
Operation Regions and Logic States
When biasing a NAND gate, you must respect the voltage thresholds. A 5V CMOS gate does not switch exactly at 2.5V; it has defined noise margins. Below are the typical operation regions for a 5V 74HC-series NAND gate.
| Parameter | Symbol | Typical Value (5V VCC) | Guaranteed Limit | Bench Note |
|---|---|---|---|---|
| Input LOW Voltage | V_IL | 1.0V | Max 1.5V | Anything below 1.5V is safely read as a 0. |
| Input HIGH Voltage | V_IH | 4.0V | Min 3.5V | Anything above 3.5V is safely read as a 1. |
| Output LOW Voltage | V_OL | 0.1V | Max 0.33V | Measured at 4mA sink current. |
| Output HIGH Voltage | V_OH | 4.9V | Min 4.67V | Measured at 4mA source current. |
| Quiescent Current | I_CC | 0.02 mA | Max 0.08 mA | Current drawn when outputs are stable. |
| Propagation Delay | t_pd | 12 ns | Max 18 ns | Time from input edge to output edge. |
If you drive an input with a voltage between 1.5V and 3.5V, both the PMOS and NMOS networks will partially turn on. This creates a direct, low-resistance path from VCC to GND inside the silicon, causing a massive spike in current that can thermally destroy the chip.
Building a Discrete NAND Gate: Application Circuit
Sometimes you need a NAND gate that operates at 12V or 24V, far exceeding the 5V limit of standard logic ICs. You can build a discrete nand transistor level circuit on a breadboard. Here is a complete application circuit designed to debounce two 12V industrial limit switches and drive a 12V relay.
Component List & Values
- Q1, Q2 (PMOS): BS250 (Vds = -45V, Id = -220mA). Sources tied to 12V.
- Q3, Q4 (NMOS): 2N7000 (Vds = 60V, Id = 200mA). Q3 drain tied to Q4 source.
- R1, R2 (Input Pulldowns): 10kΩ. Tied from inputs to GND to prevent floating gates.
- R3, R4 (Gate Resistors): 100Ω. Placed in series with the switch inputs to dampen high-frequency ringing from long cable runs.
- Q5 (Driver): 2N2222 NPN BJT. Base connected to the NAND output via a 1kΩ resistor.
- K1 (Load): 12V DC Relay coil with a 1N4007 flyback diode across the pins.
Wiring Steps
- Connect the sources of Q1 and Q2 to your 12V supply rail.
- Wire the drains of Q1 and Q2 together. This junction is your logic output.
- Connect the drain of Q3 to the output junction. Connect the source of Q3 to the drain of Q4.
- Connect the source of Q4 to Ground.
- Wire your limit switches to the gates of the MOSFETs through the 100Ω gate resistors.
- Connect the 10kΩ pulldown resistors from each gate to Ground.
- Run the output junction through a 1kΩ resistor to the base of the 2N2222 driver transistor.
- Place the relay coil between 12V and the collector of the 2N2222. Tie the emitter to Ground.
When both limit switches close (Inputs HIGH), the output node is pulled to ground, turning off the 2N2222 and de-energizing the relay. If either switch opens, the output goes HIGH, biasing the 2N2222 and pulling in the relay.
Selecting, Biasing, and Safe Default Part Numbers
When selecting a NAND gate for a project, your choice between discrete transistors and integrated circuits depends on your voltage and speed requirements.
Safe Default IC Part Numbers
- 74HC00: The absolute standard for 5V, high-speed CMOS logic. Pin-compatible with older 74LS00 TTL chips but draws microamps instead of milliamps. (TI SN74HC00 Datasheet)
- CD4011B (or HEF4011): The safe default for wide-voltage applications (3V to 15V). Slower propagation delay (~50ns), but excellent for battery-powered or 12V automotive circuits. (NXP HEF4011B Datasheet)
How to Bias Unused Inputs
CMOS inputs have incredibly high impedance (often >10^12 ohms). If you leave an input pin unconnected, it acts as an antenna, picking up electromagnetic interference from your bench lights or switching power supplies. This causes the internal transistors to rapidly toggle in the linear region, generating massive heat and injecting noise into your power rail.
The Rule: Never leave a CMOS input floating. Tie unused inputs directly to VCC or GND, or tie them to a used input on the same gate. Do not rely on internal pull-ups unless you are using a specialized microcontroller GPIO; standard logic ICs do not have them.
Bench Scenario: The Floating Input Catastrophe
Last year, I was helping a university student debug an ESP32-based data logger that was experiencing random brownout resets. The ESP32 was reading a 12V water pump status via an optocoupler, and the signal was being conditioned by a CD4011 NAND gate powered at 5V.
The Setup: The student used only one of the four NAND gates on the CD4011 chip. The inputs to the other three gates (pins 5, 6, 8, 9, 12, and 13) were left completely unconnected on the breadboard.
The Numbers: Using a thermal camera, the CD4011 chip surface was reading 68°C. A multimeter in series with the 5V rail showed the chip was drawing 18.5mA of quiescent current—over 300 times the datasheet maximum of 0.05mA. Furthermore, an oscilloscope probe on the 5V rail showed 400mV of high-frequency ripple.
The Outcome: The floating inputs were oscillating at roughly 3MHz. This massive current draw was causing a voltage drop across the breadboard's thin power rails, dragging the 5V supply down to 4.1V at the ESP32's VIN pin, triggering the microcontroller's brownout detector.
What Went Wrong & The Fix: The student treated the CMOS chip like an old TTL 74LS00, where unconnected inputs naturally float HIGH due to internal BJT biasing networks. We soldered 10kΩ resistors from all unused inputs to GND. The current draw immediately dropped to 0.03mA, the chip cooled to room temperature, and the ESP32 brownouts vanished.
Failure Modes and Multimeter Testing
Logic gates rarely fail gracefully. They usually fail due to electrostatic discharge (ESD) puncturing the gate oxide, or by exceeding the absolute maximum output current (typically ±25mA for 74HC series).
How to Test a Discrete MOSFET NAND Gate
If your discrete circuit is not working, isolate the transistors and use your digital multimeter (DMM) in Diode Test Mode.
- Check the Body Diodes: For the NMOS (2N7000), place the red probe on the Source and black on the Drain. You should read a forward voltage drop of ~0.5V. Reverse the probes; it should read OL (open loop). If it reads 0.00V in both directions, the transistor is shorted.
- Check Gate Leakage: Switch the DMM to the highest resistance setting (Megaohms). Measure between the Gate and Source, and Gate and Drain. It must read OL. Any reading below 10 MΩ indicates a punctured gate oxide. Throw the transistor away.
How to Test a Logic IC (74HC00 / CD4011)
Testing an integrated NAND gate requires checking for internal shorts before applying power, then verifying logic states.
- Cold Test (Power Off): Set DMM to resistance. Measure between VCC (Pin 14) and GND (Pin 7). A healthy chip reads >100kΩ. If it reads less than 50Ω, the internal power rail is shorted; the chip is dead.
- Hot Test (Power On): Apply 5V. Set DMM to DC Voltage. Ground one input of a gate and measure the output. It must read >4.6V. Tie both inputs to 5V; the output must drop below 0.3V.
- The Linear Region Check: If an output reads between 1.0V and 4.0V while powered, either the input is floating, the input signal is stuck in the undefined threshold zone, or the output transistor is partially burned out from sourcing too much current into a low-impedance load.
Understanding the nand transistor level architecture transforms these chips from mysterious black boxes into predictable, testable networks of switches. Whether you are wiring up a CD4011 for a 12V car project or debugging a noisy breadboard, respecting the CMOS voltage thresholds and input biasing rules will save you hours of chasing phantom electrical gremlins.
