A NAND gate outputs a logic LOW only when all of its inputs are HIGH. At the silicon level, this behavior is dictated by nand gate transistors—specifically, the arrangement of bipolar junction transistors (BJTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs) that pull the output node to ground or VCC. While modern designs almost exclusively use integrated CMOS chips like the 74HC00, understanding the discrete transistor implementation remains critical for custom high-voltage interfacing, repairing legacy RTL/DTL equipment, and bench-level debugging.
The direct answer to which transistors to use depends on your architecture. For discrete 5V bipolar builds, the 2N3904 (NPN BJT) is the undisputed safe default. For integrated CMOS logic, the CD4011 (4000 series) or 74HC00 (7400 series) are the standard go-to part numbers.
Transistor-Level NAND Architectures and Default Selections
Before wiring a circuit, you must select the right logic family. The internal transistor topology changes drastically between Resistor-Transistor Logic (RTL), Diode-Transistor Logic (DTL), and modern CMOS. Below is a data-dense comparison to help you select the right components for your bench or PCB.
| Logic Family | Internal Transistor Type | Safe Default Part Numbers | VCC Range | Propagation Delay | Typical Fan-Out |
|---|---|---|---|---|---|
| RTL (Discrete) | NPN BJT (Series arrangement) | 2N3904, 2N2222 | 3.0V - 5.0V | ~50 ns | 3 - 5 |
| DTL (Discrete) | NPN BJT + Signal Diodes | 2N3904 + 1N4148 | 5.0V | ~25 ns | 8 |
| CMOS (4000 Series IC) | P-Ch / N-Ch MOSFET pairs | CD4011B, MC14011B | 3.0V - 15.0V | ~50 ns (at 5V) | >50 (high impedance) |
| HC CMOS (7400 Series IC) | P-Ch / N-Ch MOSFET pairs | SN74HC00, MC74HC00 | 2.0V - 6.0V | ~10 ns (at 5V) | 10 (LSTTL compatible) |
Biasing for Switching: The BJT Operation Regions
When using discrete BJTs to build a NAND gate, you are not using them as amplifiers. You are using them as switches. This means you must bias the transistor strictly into cutoff (OFF) or saturation (ON). Allowing the transistor to linger in the active (linear) region during transitions causes excess power dissipation, thermal drift, and undefined output voltages.
Here are the target electrical characteristics for a standard small-signal NPN like the onsemi 2N3904 when used in digital logic:
| Operation Region | Base-Emitter Voltage (Vbe) | Collector-Emitter Voltage (Vce) | Collector Current (Ic) | Logic State |
|---|---|---|---|---|
| Cutoff | < 0.5V | ≈ VCC (e.g., 5.0V) | ≈ 0 mA | OFF (Output HIGH via pull-up) |
| Active (Linear) | 0.6V - 0.7V | 0.7V to VCC | β × Ib | FORBIDDEN (Causes heating) |
| Saturation | 0.7V - 0.9V | Vce(sat) ≈ 0.1V - 0.3V | Limited by external Rc | ON (Output LOW) |
To guarantee saturation, you must supply enough base current (Ib) so that the forced beta (Ic / Ib) is significantly lower than the transistor's maximum linear beta (hFE). For a 2N3904, hFE is typically 100-300. In switching applications, we design for a forced beta of 10 to 20 to ensure a hard, low-resistance ON state regardless of temperature variations.
Complete Application Circuit: 5V Discrete RTL NAND Gate
Let's build a functional two-input NAND gate using discrete components. In RTL, a NAND gate is formed by placing two NPN transistors in series between the pull-up resistor and ground. (Note: This is the opposite of an RTL NOR gate, which places transistors in parallel).
Symbol and Pinout Description
Imagine the standard NAND logic symbol (an AND gate with a bubble on the output). Internally, Q1 and Q2 are standard NPN BJTs. The collector of Q1 connects to the VCC pull-up resistor. The emitter of Q1 connects to the collector of Q2. The emitter of Q2 connects to ground. The output node is taken from the junction of the pull-up resistor and Q1's collector.
Component List and Values
- Q1, Q2: 2N3904 NPN Transistors
- Rc (Pull-up): 1kΩ (1/4W, 5% tolerance)
- Rb1, Rb2 (Base limits): 10kΩ (1/4W, 5% tolerance)
- VCC: 5.0V DC regulated supply
Wiring Steps
- Connect the VCC (5V) rail to one end of the 1kΩ pull-up resistor (Rc).
- Connect the other end of Rc to the Collector (pin 3, flat side facing you) of Q1. This junction is your Output.
- Connect the Emitter (pin 1) of Q1 directly to the Collector (pin 3) of Q2.
- Connect the Emitter (pin 1) of Q2 to the system Ground (GND).
- Connect Input A to one end of Rb1 (10kΩ), and the other end of Rb1 to the Base (pin 2) of Q1.
- Connect Input B to one end of Rb2 (10kΩ), and the other end of Rb2 to the Base (pin 2) of Q2.
Circuit Verification and Bias Math
When both Input A and Input B are driven HIGH (5V), both transistors turn on. Let's verify the bias math to ensure Q1 and Q2 hit hard saturation. When both are ON, Q2 drops about 0.2V (Vce_sat), and Q1 drops another 0.2V. The total voltage drop to ground is 0.4V. The current through the 1kΩ pull-up resistor (Ic) is (5V - 0.4V) / 1000Ω = 4.6 mA.
Looking at the base of Q1: The emitter of Q1 sits at 0.2V (the Vce_sat of Q2). Therefore, the base of Q1 needs to be at roughly 0.9V (0.2V + 0.7V Vbe) to conduct. The voltage drop across Rb1 is 5V - 0.9V = 4.1V. The base current (Ib) is 4.1V / 10,000Ω = 0.41 mA.
The forced beta is Ic / Ib = 4.6 mA / 0.41 mA = 11.2. Because 11.2 is vastly lower than the 2N3904's minimum hFE of 100, the transistor is driven deep into saturation, yielding a crisp, solid LOW output.
Failure Modes and Multimeter Diagnostics
Transistors in logic gates rarely fail without a physical cause. Understanding how they break helps you isolate faults on a PCB without blindly desoldering components. For deeper theoretical background on logic gate behaviors, the All About Circuits logic gate tutorial provides excellent baseline schematics.
Common Failure Mechanisms
- Thermal Runaway (Discrete BJT): If the base current is too low, the transistor operates in the active region. It acts as a variable resistor, dissipating heavy power (P = Vce × Ic). The silicon heats up, which lowers the Vbe threshold, drawing more current, until the junction melts.
- Secondary Breakdown (Discrete BJT): Caused by exceeding the Vceo rating while simultaneously passing high current. The silicon develops localized hot spots that permanently short the collector to the emitter.
- Gate Oxide Punch-Through (CMOS ICs): If you are using a 74HC00 and apply an input voltage higher than VCC + 0.5V, or subject the pins to ESD without series resistance, the microscopic gate oxide layer ruptures. This results in a permanent short or a massive increase in quiescent current draw.
How to Test NAND Gate Transistors with a Multimeter
You can test discrete BJTs in-circuit (with power removed) or out-of-circuit using your digital multimeter's Diode Test mode. If testing an IC like the Texas Instruments SN74HC00, you cannot probe internal MOSFETs directly; you must test for input-to-output shorts and verify logic truth tables with power applied.
Step-by-Step Discrete BJT Testing (Out of Circuit):
- Set your multimeter to Diode Test mode (the symbol with an arrow and a line).
- Place the Red probe on the Base and the Black probe on the Emitter. You should read a forward voltage drop between 0.600V and 0.750V.
- Swap the probes (Black on Base, Red on Emitter). The meter should read OL (Open Loop / Over Limit).
- Repeat the process between the Base and Collector. Forward bias should read 0.600V - 0.750V; reverse bias should read OL.
- Place probes across Collector and Emitter in both directions. Both must read OL. If you read a short (near 0.000V) or a low resistance, the transistor has suffered secondary breakdown and is dead.
By mastering the biasing math and recognizing the physical signatures of saturation versus active-region failure, you can reliably design custom discrete logic or confidently troubleshoot legacy NAND gate transistor arrays on the bench.
