A "NAND gate transistor" is not a single off-the-shelf component. The term refers either to the discrete transistors (BJTs or MOSFETs) wired together to form a NAND logic function on a breadboard, or to the internal silicon topology of a standard logic IC. If you need a reliable, space-saving NAND gate for a production PCB, the safe default is the 74HC00 quad 2-input NAND IC. However, if you are building a custom discrete logic interface, driving high-voltage loads directly from logic, or learning semiconductor behavior on the bench, you will wire individual transistors into a CMOS or Diode-Transistor Logic (DTL) topology.
This guide covers the exact transistor part numbers, operating regions, and biasing requirements for building discrete NAND gates, alongside bench-tested multimeter diagnostics for when your logic levels fail.
Discrete NAND Gate Transistor Topologies & Operating Regions
When building a NAND gate from discrete components, you generally choose between two topologies: CMOS (using complementary N-channel and P-channel MOSFETs) or DTL/RTL (using NPN BJTs and diodes/resistors). CMOS is vastly superior for modern bench projects due to its near-zero static power draw and rail-to-rail output swing, while BJT implementations are mostly reserved for educational demonstrations or specific high-current analog-digital interfacing.
Pinout and Symbol Basics
For the TO-92 packaged MOSFETs used in discrete CMOS logic (like the 2N7000 and BS250), hold the flat face toward you with the leads pointing down. The pinout from left to right is Source (S), Gate (G), Drain (D). For the standard 2N3904 NPN BJT in a TO-92 package, the pinout is Emitter (E), Base (B), Collector (C). In schematic symbols, the MOSFET gate is isolated from the channel by a solid line, while the BJT base connects directly to the collector-emitter path with an arrow indicating conventional current flow.
Understanding how these devices transition between cutoff and saturation is critical for clean logic switching. The table below details the operating regions and typical biasing voltages for the most common discrete transistors used in NAND gates.
| Device Type & Part | Logic State | Control Voltage (V_GS or V_BE) | Channel/Region State | Typical I_D or I_C | V_DS(sat) or V_CE(sat) |
|---|---|---|---|---|---|
| N-MOSFET (2N7000) | Logic 0 (OFF) | 0.0V | Cutoff | < 1 µA (leakage) | N/A (Blocking) |
| N-MOSFET (2N7000) | Logic 1 (ON) | 5.0V | Ohmic (Linear) | Load dependent | ~1.2 Ω (R_DS(on)) |
| P-MOSFET (BS250) | Logic 0 (ON) | -5.0V (Gate at 0V) | Ohmic (Linear) | Load dependent | ~3.0 Ω (R_DS(on)) |
| P-MOSFET (BS250) | Logic 1 (OFF) | 0.0V (Gate at 5V) | Cutoff | < 1 µA (leakage) | N/A (Blocking) |
| NPN BJT (2N3904) | Logic 0 (OFF) | < 0.5V | Cutoff | < 50 nA | N/A (Blocking) |
| NPN BJT (2N3904) | Logic 1 (ON) | ~0.7V (Forward biased) | Saturation | Load dependent | ~0.2V |
Building a 2-Input Discrete CMOS NAND Gate
The most robust way to build a discrete NAND gate transistor circuit is using a complementary MOSFET (CMOS) topology. This configuration uses two P-channel MOSFETs in parallel for the pull-up network and two N-channel MOSFETs in series for the pull-down network. It draws virtually zero static current and provides a strong logic HIGH and LOW.
Components: 2x 2N7000 (N-ch), 2x BS250 (P-ch), 1x 10kΩ pull-down resistor (optional, for floating input protection), 5V DC supply.
Target Output: Logic LOW only when BOTH inputs are HIGH.
Step-by-Step Wiring Procedure
- Prepare the Pull-Up Network: Insert the two BS250 P-channel MOSFETs into the breadboard. Connect both of their Source pins directly to the 5V positive rail.
- Tie the Outputs: Connect the Drain pin of the first BS250 to the Drain pin of the second BS250. This shared node is your Logic Output (Y).
- Route the Inputs (Pull-Up): Connect the Gate of the first BS250 to Input A. Connect the Gate of the second BS250 to Input B.
- Prepare the Pull-Down Network: Insert the two 2N7000 N-channel MOSFETs. Connect the Drain of the top 2N7000 to the shared Logic Output (Y) node.
- Stack the N-Channel FETs: Connect the Source of the top 2N7000 to the Drain of the bottom 2N7000. This series connection is what creates the AND logic required for the NAND inversion.
- Ground the Network: Connect the Source of the bottom 2N7000 directly to the GND rail.
- Route the Inputs (Pull-Down): Connect the Gate of the top 2N7000 to Input A. Connect the Gate of the bottom 2N7000 to Input B.
- Verify: Apply 5V to A and B. Output should read ~0V. Ground either A or B. Output should snap to ~5V.
Biasing, Selection, and Safe Default Part Numbers
When selecting transistors for discrete logic, threshold voltage (V_GS(th) for MOSFETs, V_BE for BJTs) is your primary biasing constraint. If your driving microcontroller outputs 3.3V logic, a standard BJT will switch fine, but some high-threshold power MOSFETs will remain in the linear region, causing massive heat dissipation and undefined logic levels. Always select logic-level or small-signal transistors for gate building.
| Category | Safe Default Part Number | Key Ratings | Best Use Case |
|---|---|---|---|
| Standard IC (Quad NAND) | SN74HC00N (TI) | VCC: 2V-6V, I_out: 25mA, t_pd: 14ns | 99% of digital logic PCB designs. |
| Discrete N-Channel MOSFET | 2N7000 (ON Semi) | V_DS: 60V, I_D: 200mA, V_GS(th): 0.8V-3.0V | Bench CMOS builds, 5V/3.3V logic translation. |
| Discrete P-Channel MOSFET | BS250 (Diodes Inc.) | V_DS: -45V, I_D: -230mA, V_GS(th): -1.0V to -3.5V | Complementary pull-up networks in discrete CMOS. |
| Discrete NPN BJT | 2N3904 (ON Semi) | V_CEO: 40V, I_C: 200mA, h_FE: 100-300 | DTL/RTL educational builds, low-side switching. |
Reference: For exact timing and DC characteristics of the IC equivalent, consult the Texas Instruments SN74HC00 Datasheet. For discrete MOSFET threshold curves, see the ON Semiconductor 2N7000 Datasheet.
When to Choose Discrete vs. IC
Choose the 74HC00 IC when you need multiple gates, high switching speeds (MHz range), and tight propagation delay matching. Choose discrete transistors when you need to drive a highly inductive load directly from the logic gate (using beefier MOSFETs like the IRF520 in the pull-down network), when you are operating in high-radiation environments where discrete components fail gracefully compared to dense silicon, or when you are troubleshooting fundamental semiconductor theory.
Failure Modes and Multimeter Testing
Discrete transistors in logic gates typically fail in three ways: Gate oxide punch-through (MOSFETs destroyed by ESD, resulting in a shorted gate), thermal runaway (BJTs left in the linear region due to poor biasing, melting the junction), and overcurrent shorts (drain-to-source or collector-to-emitter shorting out due to exceeding load limits).
You do not need an oscilloscope to diagnose a dead NAND gate transistor. A standard digital multimeter (DMM) in Diode Test Mode is sufficient to isolate the fault.
How to Test an N-Channel MOSFET (2N7000)
- Discharge the Gate: Touch your finger across the Gate and Source pins simultaneously to bleed off any static charge that might be holding the channel open.
- Test the Body Diode: Set your DMM to Diode Test. Place the Black (COM) probe on the Source and the Red probe on the Drain. You should read a forward voltage drop between 0.45V and 0.65V.
- Test Reverse Blocking: Swap the probes (Red to Source, Black to Drain). The meter should read OL (Open Loop).
- Test Channel Switching: Keep the Black probe on the Source. Briefly touch the Red probe to the Gate to charge it. Then move the Red probe to the Drain. The meter should now read near 0.00V (or a very low resistance), indicating the channel has turned ON.
- Verify Turn-Off: Discharge the gate again (finger across G-S). Re-test Step 3; it should return to OL.
How to Test an NPN BJT (2N3904)
- Base-Emitter Junction: DMM in Diode Test. Red probe to Base, Black to Emitter. Expect 0.60V to 0.75V. Reverse probes: expect OL.
- Base-Collector Junction: Red probe to Base, Black to Collector. Expect 0.60V to 0.75V. Reverse probes: expect OL.
- Collector-Emitter Isolation: Place probes across Collector and Emitter in both directions. Both must read OL. If you read a short (0.00V) or a low resistance in either direction, the transistor has suffered a thermal junction failure and must be replaced.
By mastering these discrete topologies and bench-testing techniques, you can debug custom logic interfaces and understand the exact silicon behavior that standard ICs hide behind their plastic packages.
