The standard multiplexer (MUX) symbol in modern schematics is a rectangular block defined by IEEE Std 91a-1991 and IEC 60617, featuring data inputs on the left, select/address lines on the bottom or side, and a single output on the right. Whether you are designing an ESP32 sensor array using a 74HC4051 or troubleshooting a legacy 74LS157 digital logic board, correctly interpreting the symbol's dependency notation and enable bubbles is critical to avoiding dead shorts or floating inputs.
The Complete Multiplexer Symbol & Pin Reference Table
The table below maps the graphical elements you see on a schematic to their physical pin functions. This applies to both digital logic multiplexers (like the 74HC157) and analog signal multiplexers (like the CD4052B).
| Symbol Element / Pin Designator | Standard Name (IEEE/IEC) | Function in Practice | Common IC Equivalent |
|---|---|---|---|
| D0–Dn or I0–In | Data Inputs / Channels | The source signals. In analog MUXes, these are bidirectional I/O channels. | Pins 13, 14, 15, 12, 1, 5, 2, 4 on 74HC4051 |
| S0–Sn or A0–An | Select / Address Lines | Binary control lines that route a specific input to the output. S0 is always the LSB. | Pins 11 (A), 10 (B), 9 (C) on 74HC4051 |
| Y or Z | Output / Common Pin | The single routed signal. 'Z' denotes a high-impedance state when disabled. | Pin 3 (COM) on 74HC4051 |
| E, EN, or INH | Enable / Inhibit | Master switch for the IC. Often active-low (indicated by a bubble or overline). | Pin 6 (INH) on 74HC4051 |
| VCC / VDD | Positive Supply | Logic high reference. For analog MUXes, sets the maximum passable voltage. | Pin 16 |
| GND / VSS | Ground / Negative Supply | Logic ground. Analog MUXes may have a separate VEE for negative signal rails. | Pin 8 (GND), Pin 7 (VEE) |
Regional and Standard Variants (IEEE vs. IEC vs. Legacy)
Schematic symbols for multiplexers vary depending on the drafting standard used by the original engineer. While the underlying silicon remains identical, the visual representation changes.
IEEE Std 91a-1991 & IEC 60617 (Modern Standard)
This is the globally accepted standard for new designs. The MUX is drawn as a tall rectangle. Inside the box, you will often see dependency notation, such as G1 or M0. For example, if the select lines are labeled A0 and A1, and the inputs are labeled 0 through 3, an internal 'G' label indicates that the select lines act as a group controller for the data paths. This standard is heavily used in modern digital logic textbooks and European schematic captures.
MIL-STD-806 / ANSI Y32.2 (Legacy / US Military)
If you are repairing vintage test equipment, aviation electronics, or 1980s industrial PLCs, you will encounter the trapezoid or 'wedge' shape. The wide end of the trapezoid holds the data inputs, and the narrow point is the output. Select lines protrude from the flat bottom or side. While obsolete for new designs, this symbol is still universally recognized by senior electrical engineers.
Analog Switch Representation
For analog multiplexers like the 74HC4051, designers sometimes bypass standard logic symbols entirely and draw the IC as a bank of literal SPST (Single Pole Single Throw) switches with a shared digital control line. This is common in mixed-signal audio and RF schematics to emphasize that the component passes continuous voltages, not just binary 1s and 0s.
Schematic Rows and Pins People Get Wrong
Misinterpreting a multiplexer symbol rarely destroys the component, but it will result in erratic readings, floating inputs, or complete signal loss. Watch out for these specific pitfalls:
The most common bench mistake is misreading the Enable (EN) or Inhibit (INH) pin. In IEC/IEEE symbols, a small circle (bubble) on the enable pin means active-low. If you tie an active-low INH pin (like Pin 6 on the Texas Instruments 74HC4051) directly to VCC thinking it 'enables' the chip, you are actually forcing it into a high-impedance disabled state. Always tie active-low enables to GND to turn the MUX on.
Select Line Binary Weighting (S0 vs S1)
Schematics rarely label select lines with their binary weight. By convention, S0 (or A0) is always the Least Significant Bit (LSB), and the highest number (e.g., S2) is the Most Significant Bit (MSB). If you wire your microcontroller's GPIO 5 to S2 and GPIO 4 to S0, your binary addressing will be inverted, causing you to read Channel 4 when you request Channel 1.
Digital 'Y' vs. High-Impedance 'Z' Outputs
Some advanced bus multiplexers (like the 74HC257) feature a 3-state output. If the symbol shows the output labeled as Z instead of Y, it indicates that when the enable pin is pulled inactive, the output doesn't just go to logic LOW (0V); it physically disconnects, becoming high-impedance. This is critical for shared data buses but will cause floating, noisy ADC readings if used for sensor multiplexing without a pull-down resistor.
Tracing MUX Pinouts When PCB Markings Fade
When repairing consumer electronics or industrial control boards, the silkscreen identifying the multiplexer IC is often burned off, scratched away, or obscured by conformal coating. Here is how to safely identify the pins using a multimeter:
- Locate VCC and GND: Find the 100nF decoupling capacitor nearest the IC. The capacitor's ground leg connects to the MUX GND pin (usually Pin 8 on 14/16-pin DIPs). The other leg points toward VCC (Pin 16 or 14).
- Identify the Common/Output Pin: Switch your multimeter to continuity mode. Probe the suspected output pin and trace it to the ADC input of the main microcontroller or the input of an op-amp. The common pin usually has a thicker, more direct trace than the address lines.
- Trace the Select Lines: The select lines (S0, S1, S2) will almost always route directly to general-purpose GPIO pins on a microcontroller. They rarely pass through resistors or capacitors. If you find three pins routing straight to an MCU, you have found your address bus.
- Verify the Inhibit/Enable Pin: This pin will either be tied directly to ground (permanently enabled) or routed to a single MCU GPIO. If it is tied to ground, measure the resistance to the ground plane; it should read less than 1 ohm.
Multiplexer Symbol FAQs
What does the bubble on a multiplexer enable pin mean?
A bubble (or circle) on the enable or inhibit pin indicates that the pin is active-low. This means the multiplexer is turned ON when the pin is pulled to GND (Logic 0), and turned OFF when the pin is pulled to VCC (Logic 1). If the symbol lacks a bubble, it is active-high and requires a logic 1 to operate.
How is an analog multiplexer symbol different from a digital one?
While both may use the standard IEEE rectangular block, an analog multiplexer symbol (like the 4051) will often explicitly show a VEE pin alongside VCC and GND to indicate it can pass negative voltages. Additionally, the input/output lines may be drawn with bidirectional arrows to show that analog MUXes pass signals in both directions, whereas digital MUX symbols typically show unidirectional flow from inputs to output.
Why do some multiplexer symbols show a trapezoid instead of a rectangle?
The trapezoid or wedge shape is the legacy MIL-STD-806 symbol for a multiplexer. It was standard in US military and aerospace schematics from the 1960s through the 1980s. The wide base represents the multiple data inputs, visually 'funneling' down to the single narrow output. You will still see this in older reference designs and vintage equipment manuals.
How do I read the select lines (S0, S1) on a MUX schematic?
Select lines dictate which input channel is routed to the output based on binary logic. S0 is the LSB (1s place) and S1 is the MSB (2s place). To read Channel 3 (binary 11), you must drive S1 HIGH and S0 HIGH. To read Channel 2 (binary 10), drive S1 HIGH and S0 LOW. Always verify the datasheet to confirm if the IC uses A0/A1 or S0/S1 nomenclature, though the LSB-to-MSB weighting remains universal.
