A MOSFET differential amplifier is a foundational analog circuit that uses two matched Metal-Oxide-Semiconductor Field-Effect Transistors to amplify the voltage difference between two input gates while aggressively rejecting any voltage common to both inputs. If you are building sensor interfaces, audio preamplifiers, or the input stage of a custom op-amp, this topology is your starting point. The direct answer to "why use this over a single transistor?" is Common-Mode Rejection Ratio (CMRR). A well-matched differential pair will strip out power supply noise and ground bounce that would otherwise drown out a millivolt-level sensor signal.
Unlike BJT differential pairs, the MOSFET variant offers near-infinite DC input impedance, meaning it won't load down high-impedance sources like piezo sensors or pH probes. However, achieving high CMRR on the bench requires strict attention to device matching and biasing. Below is a practical, bench-focused guide to designing, selecting parts for, and testing a discrete MOSFET long-tailed pair.
MOSFET Pinout, Symbol, and Operation Regions
Before wiring the pair, you must understand the four-terminal reality of the MOSFET. While schematics often hide the fourth terminal, it dictates your circuit's physical behavior.
- Gate (G): The voltage-controlled input. Draws virtually zero DC current, but has high parasitic capacitance.
- Drain (D): The output terminal where the amplified signal is developed across a load resistor.
- Source (S): The reference terminal for the gate voltage. In a differential pair, the sources of both transistors are tied together.
- Bulk/Body (B): The substrate connection. In discrete NMOS devices (like the 2N7000), the bulk is internally tied to the source. In IC designs or bare-die matched pairs, the bulk must be explicitly tied to the most negative potential in the circuit (usually ground) to prevent the parasitic body diode from forward-biasing.
To function as an amplifier, both MOSFETs in the differential pair must be biased squarely in the Saturation region (often called the Active region in BJT terminology). If they drift into the Triode region, your gain collapses and distortion spikes.
| Operation Region | Gate-Source Condition | Drain-Source Condition | Drain Current (Id) Behavior | Typical Bench Voltages |
|---|---|---|---|---|
| Cutoff | V_GS < V_th | Any V_DS | Id ≈ 0 (Leakage only) | V_GS = 0V, V_DS = 5V |
| Triode (Linear) | V_GS > V_th | V_DS < (V_GS - V_th) | Id acts like a voltage-controlled resistor | V_GS = 4V, V_DS = 0.5V |
| Saturation (Active) | V_GS > V_th | V_DS ≥ (V_GS - V_th) | Id is constant, controlled only by V_GS (Amplification) | V_GS = 3.5V, V_DS = 4V |
Designing and Biasing the Long-Tailed Pair
The standard MOSFET differential amplifier is known as the "long-tailed pair." The two sources are tied together and fed by a constant current source (the "tail"). When a differential voltage is applied to the gates, the tail current steers between the two transistors. If Q1 turns on harder, Q2 must turn off by the exact same amount, keeping the sum of their drain currents constant.
Complete Application Circuit: 12V Single-Supply Sensor Preamp
Here is a proven, breadboard-friendly component list for a 12V NMOS differential amplifier targeting a quiescent drain current (Id) of 1mA per transistor.
- Q1, Q2 (Matched Pair): ALD1101 (Pins: Q1 D=2, G=3, S=4; Q2 D=6, G=5, S=4. Bulk tied to Pin 7/GND).
- R_D1, R_D2 (Drain Load Resistors): 4.7kΩ (1% metal film). Drops ~4.7V at 1mA, leaving plenty of V_DS headroom for saturation.
- Q_Tail (Constant Current Source): 2N5457 JFET. Configured as a current sink.
- R_S_Tail (JFET Source Resistor): 470Ω. Sets the JFET tail current to approximately 2mA (1mA per side).
- R_G1, R_G2 (Gate Bias Resistors): 1MΩ to GND. Provides a DC return path for the high-impedance gates.
Biasing Calculations
To keep Q1 and Q2 in saturation, we must verify V_DS. With a 12V supply and a 4.7kΩ drain resistor dropping 4.7V, the drain sits at 7.3V. The sources sit at roughly 1.5V (determined by the gate bias and V_th). Therefore, V_DS = 7.3V - 1.5V = 5.8V. Since 5.8V is well above the overdrive voltage (V_GS - V_th), the transistors are safely in saturation. For a deeper theoretical breakdown of input stage topologies, refer to the TI Precision Labs Op-Amp series, which details how these discrete principles scale into monolithic IC design.
Selecting Safe Default Part Numbers
The Achilles heel of the MOSFET differential amplifier is mismatch. If Q1 and Q2 have different threshold voltages (V_th), the circuit will suffer from input offset voltage, ruining your CMRR. Never use two random discrete transistors from a bin and expect precision. Use monolithic matched pairs.
| Part Number | Type | Max V_DS | Max I_D | V_GS(th) Range | Best Application |
|---|---|---|---|---|---|
| ALD1101 | Quad NMOS (Matched) | 10.6V | 30mA | 0.4V to 1.0V | Precision sensor amps, low-voltage audio. |
| CD4007UB | Hex MOSFET Array | 15V | 10mA | 1.5V to 3.5V | Prototyping, educational labs, mixed-signal. |
| 2N7000 | Discrete NMOS | 60V | 200mA | 0.8V to 3.0V | Crude demonstrations only (poor matching). |
| DMOS100 | Dual NMOS (Matched) | 20V | 500mA | 0.7V to 1.5V | Higher current RF mixers, power stages. |
Note: Always consult the specific manufacturer datasheet for the CD4007UB or ALD1101 before wiring, as pinouts for multi-transistor arrays vary wildly between the DIP-14 and SOIC-14 packages.
Failure Modes and Multimeter Testing
MOSFETs in differential configurations typically fail in two ways: Gate Oxide Punch-Through and Thermal Runaway. The gate oxide layer is microscopically thin; a static shock from your finger can easily exceed its 20V breakdown limit, creating a permanent short between the gate and source. Thermal runaway occurs if the devices are not thermally coupled; as one heats up, its V_th drops, causing it to hog more of the tail current, heating up further until it destroys itself.
How to Test a MOSFET with a Digital Multimeter
Before soldering your matched pair into the circuit, verify it hasn't been killed by ESD in the parts drawer. Set your DMM to Diode Test Mode.
- Discharge the Gate: Briefly short all three pins (G, D, S) together with a piece of bare wire or a 1MΩ resistor to bleed off any trapped gate charge.
- Test the Body Diode (NMOS): Place the Red probe on the Source and the Black probe on the Drain. You should read a forward voltage drop of 0.4V to 0.7V. Reverse the probes (Red on Drain, Black on Source); the meter should read "OL" (Open Loop).
- Check for Gate Punch-Through: Place the Red probe on the Gate and the Black probe on the Source. The meter MUST read "OL". If you read any continuity or a diode drop, the gate oxide is punctured. Throw the part away.
- Check Gate-to-Drain Leakage: Place the Red probe on the Gate and the Black probe on the Drain. Again, this must read "OL".
- Functional Turn-On Test: While keeping the Black probe on the Source, touch the Red probe to the Gate to charge it. Then move the Red probe back to the Drain. The meter should now read a low voltage drop (near 0V), indicating the MOSFET has turned on and is conducting in the triode region. Short G to S again to turn it off.
By selecting a monolithic matched pair, biasing the drains to leave adequate V_DS headroom, and rigorously testing for gate leakage before assembly, your MOSFET differential amplifier will deliver the high CMRR and low noise floor required for precision analog work.
