A MOSFET current mirror copies a reference current to one or more output branches by matching the gate-source voltage (VGS) of identical transistors. For a reliable 5mA hobbyist mirror, the CD4007UB (rated for 15V max, containing matched N-channel and P-channel pairs) is the safest default IC, typically biased with a 2kΩ reference resistor on a 12V rail. Unlike BJT mirrors, MOSFET versions suffer virtually zero gate current leakage, making them ideal for high-impedance biasing networks and low-power sensor interfaces.
The Core Concept and Symbol Pinout
At its most basic, a current mirror consists of two transistors. To understand the symbol and pinout, visualize two N-channel enhancement MOSFETs (Q1 and Q2) sharing a common substrate and source connection.
- Q1 (The Reference): The Gate and Drain pins are tied together (diode-connected). The Source connects to Ground. The Drain receives the reference current (IREF).
- Q2 (The Mirror): The Gate is tied directly to Q1's Gate. The Source connects to Ground. The Drain acts as the output, sinking the mirrored current (IOUT) from your load.
Because both transistors share the same Gate-Source voltage (VGS) and are physically identical, they attempt to draw the exact same Drain current. If Q1 is forced to conduct 5mA by an external resistor, Q2 will sink 5mA from whatever load is attached to its drain, provided Q2 remains in the correct operating region.
Operation Regions and Biasing Strategy
A common bench mistake is allowing the mirroring transistor (Q2) to fall out of saturation. For a MOSFET to act as a current source, it must operate in the Saturation (or Active) region. If the voltage across Q2's Drain-Source (VDS) drops too low, it enters the Triode region and behaves like a voltage-controlled resistor, destroying the current mirror effect.
| Region | VGS Condition | VDS Condition | Typical VDS / ID | Mirror Status |
|---|---|---|---|---|
| Cutoff | VGS < VTH | Any | 0V / 0mA | Off (No mirror) |
| Triode (Linear) | VGS > VTH | VDS < (VGS - VTH) | < 1.0V / Varies | Failed (Acts as resistor) |
| Saturation (Active) | VGS > VTH | VDS ≥ (VGS - VTH) | > 1.5V / Constant | Active (Stable mirror) |
Biasing for Stability: To bias the mirror, you place a resistor (RREF) between your positive supply (VDD) and Q1's Drain. The value is calculated as: RREF = (VDD - VGS) / IREF. You must ensure the load attached to Q2 leaves enough voltage headroom so that VDS2 stays above the saturation threshold (VGS - VTH).
A Complete, Bench-Tested Application Circuit
Let's build a 5mA constant current sink to drive an LED or bias a transistor stage, using a 12V supply. We will use the CD4007UB IC, which guarantees matched threshold voltages (VTH) between its internal transistors.
Circuit Parameters & Assumptions:
- VDD = 12.0V DC
- Target IOUT = 5.0mA
- CD4007UB typical VTH = 1.5V
- Estimated VGS at 5mA = 2.5V (derived from datasheet transfer curves)
Component Values:
- RREF: (12V - 2.5V) / 0.005A = 1,900Ω. Use a standard 2kΩ 1/4W metal film resistor (yields ~4.75mA).
- Q1 & Q2: Pins 6 & 8 (Sources to GND), Pin 7 (Q1 Drain), Pin 8 (Q2 Drain), Pins 9 & 10 (Gates tied together and to Pin 7).
Build and Verify Steps:
- Insert the CD4007UB across the breadboard center trench. Connect Pin 14 to +12V and Pin 7 to Ground (Note: Pin 7 is the substrate tie for the N-channel pair; verify your specific datasheet, as CD4007 pinouts can vary slightly by manufacturer. Standard TI pinout uses Pin 8 for VSS/GND and Pin 14 for VDD. For the N-channel pair: Sources=Pin 8, Q1 Drain=Pin 6, Q2 Drain=Pin 1, Gates=Pin 2 & 3. Always consult the physical datasheet for your exact manufacturer).
- Tie the Gate and Drain of Q1 together. Connect RREF (2kΩ) from +12V to Q1's Drain.
- Connect the Gate of Q2 to the Gate of Q1.
- Connect your load (e.g., an LED with a 100Ω safety resistor) from +12V to Q2's Drain.
- Power the circuit and use a multimeter in series with Q2's drain to verify the current reads between 4.5mA and 5.0mA.
Selecting Safe Default Part Numbers
Never use two random discrete MOSFETs (like two IRF520s) for a precision current mirror. Discrete power MOSFETs have massive VTH tolerances (often ±1V). If Q1 has a VTH of 2.0V and Q2 has a VTH of 3.0V, your mirror will fail drastically. Always use monolithic matched pairs.
- CD4007UB (Texas Instruments / ON Semi): The ultimate hobbyist default. Rated for 15V VDD max and ~10mA continuous drain current. Contains three N-channel and three P-channel MOSFETs on a single die, ensuring excellent thermal and electrical matching. Cost: ~$0.50.
- ALD1101 (Advanced Linear Devices): A precision matched N-channel pair. VTH is matched to within 10mV. Rated for 10.6V VDS max and 30mA ID. Ideal for low-voltage, high-precision analog sensor circuits. Cost: ~$2.50.
- ALD1102 (Advanced Linear Devices): The P-channel complement to the ALD1101. Use this when you need a high-side current source rather than a low-side sink. Rated similarly at 10.6V and 30mA.
Failure Modes and Multimeter Testing
When a MOSFET current mirror fails on the bench, it usually stems from one of three issues. Here is how to diagnose them using a standard digital multimeter (DMM).
1. Gate Oxide Punch-Through (ESD Damage)
- Symptom: The mirror draws maximum current regardless of RREF, or draws zero current.
- DMM Test: Set DMM to resistance mode (20MΩ range). Measure between Gate and Source. A healthy MOSFET reads infinite (OL). If it reads a low resistance or a dead short, the gate oxide is ruptured. Discard the IC.
2. Triode Region Clipping (Headroom Loss)
- Symptom: IOUT is significantly lower than IREF and fluctuates with load changes.
- DMM Test: Set DMM to DC Voltage. Measure VDS across Q2. If VDS is less than 1.5V (assuming a 2.5V VGS), Q2 has fallen into the triode region. Fix: Increase VDD or reduce the load resistance.
3. Thermal Runaway (Mismatched Heating)
- Symptom: Current starts accurate but slowly drifts upward over 60 seconds.
- Cause: MOSFETs have a negative temperature coefficient for VTH at low currents. If Q2 dissipates more heat than Q1, its VTH drops, causing it to draw more current, creating a runaway loop. In monolithic ICs like the CD4007, the die is thermally coupled, preventing this. If using discrete TO-220 packages, you must physically bolt them to the same heatsink.
Frequently Asked Questions
Why is my discrete MOSFET current mirror outputting the wrong current?
If you built a mirror using two separate 2N7000 or IRF540N transistors, the error is almost certainly due to threshold voltage (VTH) mismatch. Discrete MOSFETs are binned for minimum RDS(on) and maximum current, not for matched VTH. A mere 200mV difference in VTH between Q1 and Q2 can cause a 30% error in the mirrored current due to the square-law transfer characteristic of the MOSFET. To fix this, switch to a monolithic matched pair IC like the CD4007UB or ALD1101, or add a small source-degeneration resistor (e.g., 10Ω to 47Ω) to each source pin to swamp out the VTH differences.
How do I increase the output impedance of a MOSFET current mirror?
A basic two-transistor mirror has a finite output impedance due to channel-length modulation (the Early effect equivalent in MOSFETs). As VDS increases, the current creeps up slightly. To achieve a near-infinite output impedance, build a Wilson Current Mirror or a Cascode Current Mirror. A cascode configuration stacks a third MOSFET on top of Q2's drain, holding Q2's VDS constant regardless of the load voltage. This requires an additional bias voltage rail but increases the output impedance by a factor of 100 or more, making it ideal for precision DACs and high-gain amplifier loads.
Can I use a MOSFET current mirror for high-side switching?
Yes, but you must use P-channel MOSFETs instead of N-channel. In a high-side PMOS mirror, the Sources connect to VDD, and the reference resistor (RREF) connects from Q1's Drain to Ground. The mirrored current flows out of Q2's Drain into the load, which is then tied to Ground. The ALD1102 is an excellent default part for this. Keep in mind that PMOS transistors generally have higher on-resistance and lower mobility than NMOS, so high-side mirrors are better suited for low-current biasing (under 20mA) rather than driving heavy loads.
