Op amp loop gain ($A\beta$) is the difference between what the amplifier can do (open-loop gain, $A$) and what the feedback network forces it to do (closed-loop gain, $1/\beta$). It is the single most critical metric for predicting bandwidth, distortion, and stability in linear circuits. If your loop gain drops below 20dB at your operating frequency, your circuit will exhibit severe non-linearities, and if the phase margin collapses, it will oscillate. Understanding this parameter separates hobbyists who blindly copy schematics from engineers who design predictable, stable analog front-ends.
The Anatomy of Loop Gain: Pinouts and Operating Regions
Before calculating loop gain, you must understand the physical device. The standard 8-pin DIP or SOIC operational amplifier follows a universal pinout convention. Pin 2 is the Inverting Input (IN-), Pin 3 is the Non-Inverting Input (IN+), Pin 4 is V- (negative rail or ground), Pin 6 is the Output, and Pin 7 is V+ (positive rail). Pins 1 and 5 are typically offset null or no-connect, and Pin 8 is usually no-connect.
The op-amp operates in distinct regions depending on the differential voltage between IN+ and IN- and the available loop gain. Here is how those regions manifest on the bench:
| Operation Region | Differential Input Voltage | Output State | Loop Gain Status |
|---|---|---|---|
| Linear (Active) | < 1mV (Virtual Short) | Within rails (V- + 1V to V+ - 1V) | High ($A\beta > 20dB$) |
| Positive Saturation | IN+ > IN- by > 5mV | Clamped near V+ rail | Zero (Feedback broken) |
| Negative Saturation | IN- > IN+ by > 5mV | Clamped near V- rail | Zero (Feedback broken) |
| Slew-Rate Limited | Large signal step applied | Ramping at max $dV/dt$ | Temporarily collapsed |
Selecting and Biasing the Right Op-Amp for the Job
Selecting an op-amp requires matching the Gain-Bandwidth Product (GBP) to your required closed-loop gain and maximum signal frequency. Biasing dictates how you set the DC operating point. For dual-supply designs (e.g., ±15V), the inputs naturally sit near 0V (ground). For single-supply designs (e.g., 0V to 5V), you must create a mid-supply virtual ground (e.g., 2.5V) using a resistor divider buffered by another op-amp, otherwise your AC signal will clip on the negative half-cycle.
Here are the safe default part numbers I keep in my bench drawer, complete with their critical ratings and 2026 approximate single-unit pricing:
- LM358: The universal low-cost workhorse. GBP: 1 MHz. Supply: 3V to 32V (single or dual). Slew rate: 0.5 V/µs. Price: ~$0.15. Use for slow DC sensors, LED drivers, and non-critical audio.
- TL072: The JFET-input standard for general audio. GBP: 3 MHz. Supply: ±5V to ±18V. Slew rate: 13 V/µs. Price: ~$0.60. Excellent for guitar pedals and mixing consoles.
- NE5532: The high-current audio driver. GBP: 10 MHz. Supply: ±5V to ±15V. Slew rate: 9 V/µs. Price: ~$0.85. Capable of driving 600Ω headphones directly.
- OPA2134: Precision FET-input for high-impedance sources. GBP: 8 MHz. Supply: ±2.5V to ±18V. Slew rate: 20 V/µs. Price: ~$4.50. Ideal for piezo sensors and studio DAC outputs.
A Complete Application Circuit: Non-Inverting Amplifier
Let us build a non-inverting amplifier with a closed-loop gain of 20dB (10 V/V) to amplify a 100mV AC sensor signal to 1V. We will use the NE5532 on a ±12V dual supply.
Component Values:
- U1: NE5532 (Pins 4 to -12V, Pin 8 to +12V, Pin 3 to sensor signal)
- R1 (Ground to IN-): 1kΩ (1% metal film)
- R2 (Output to IN-): 9kΩ (1% metal film)
- C1 (Input coupling): 1µF film capacitor (blocks DC offset from sensor)
- C2, C3 (Decoupling): 100nF MLCC placed within 5mm of Pins 4 and 8 to ground.
Loop Gain Calculation:
The feedback factor $\beta$ is determined by the voltage divider at the inverting input: $\beta = R1 / (R1 + R2) = 1000 / 10000 = 0.1$.
The NE5532 has a typical DC open-loop gain ($A$) of 100,000 V/V (100dB).
Therefore, the DC loop gain is $A\beta = 100,000 \times 0.1 = 10,000$ (80dB).
This massive 80dB of loop gain forces the output to perfectly track the input, reducing the op-amp's native Total Harmonic Distortion (THD) by a factor of 10,000. According to Texas Instruments Precision Labs, this high loop gain is exactly what yields the ultra-low 0.002% THD characteristic of the NE5532.
Bench Scenario: When Loop Gain Collapses (And What Went Wrong)
Theory is clean; the bench is unforgiving. Last year, I was tasked with debugging an ultrasonic distance sensor front-end that kept dropping its phase-locked loop (PLL) lock at exactly 40kHz. The schematic called for a microphone preamp with a gain of 40dB (100 V/V).
The Setup: The original designer used an LM358 to save $0.40 per board. The circuit was a standard non-inverting topology with a gain of 100.
The Numbers: The LM358 has a GBP of 1 MHz. The open-loop gain ($A$) rolls off at 20dB/decade. At our target frequency of 40kHz, the available open-loop gain is $1,000,000 / 40,000 = 25$ V/V (28dB).
The Outcome: We needed a closed-loop gain of 100 V/V (40dB), but the op-amp only had 25 V/V of open-loop gain available. The loop gain ($A\beta$) was $25 / 100 = 0.25$ (negative 12dB). Because the loop gain was less than 1, the LM358 physically could not achieve the 40dB gain. The output was severely attenuated, and the phase shift at 40kHz was massive, completely destroying the PLL timing.
What Went Wrong & The Fix: The designer looked at the DC gain on the datasheet and ignored the AC loop gain. I replaced the LM358 with an AD8065 (GBP 143MHz, $3.20). At 40kHz, the AD8065 provides over 70dB of open-loop gain, yielding a healthy 30dB of loop gain. The amplifier hit exactly 40dB of closed-loop gain, phase shift dropped to near zero, and the sensor locked instantly. Always verify your loop gain at your maximum operating frequency, not just at DC.
Troubleshooting: How Op-Amps Fail and Multimeter Testing
Op-amps rarely fail gracefully. The most common failure modes are Electrical Overstress (EOS) from hot-plugging inductive loads, latch-up from input voltages exceeding the supply rails, and thermal shutdown from driving heavy capacitive loads without an isolation resistor.
If you suspect a dead op-amp on a populated PCB, you can perform a highly reliable diagnostic using a standard digital multimeter (DMM) without desoldering the chip, provided the board is completely de-energized.
- Isolate the Power: Disconnect all power sources and discharge any bulk capacitors. Verify 0V across the V+ and V- pins with the DMM in voltage mode.
- Test Input Protection Diodes: Set your DMM to Diode Test mode. Place the red probe on the IN- pin (Pin 2) and the black probe on the V- pin (Pin 4). You should read a forward voltage drop between 0.6V and 0.8V. Reverse the probes; it should read 'OL' (Open Loop). Repeat for IN+ (Pin 3). A reading of 0.0V indicates a blown ESD diode (EOS damage).
- Test the Output Stage: Keep the DMM in Diode Test mode. Place the red probe on the Output pin (Pin 6) and the black probe on V+ (Pin 8). Read the PNP pull-up transistor junction (expect ~0.6V). Swap probes to read the NPN pull-down junction to V-. If both directions read 'OL', the output bond wire has likely fused open due to a short circuit.
- Verify Feedback Network: Switch the DMM to Resistance mode. Measure across R1 and R2 in-circuit. If your loop gain calculations are correct but the circuit is oscillating, a hairline fracture in a surface-mount feedback resistor will drop $\beta$ to zero, forcing the op-amp into open-loop saturation.
Mastering op amp loop gain requires shifting your perspective from DC idealizations to AC realities. By calculating $A\beta$ at your signal frequency, selecting parts with adequate GBP, and rigorously testing the silicon when things go wrong, you will eliminate the vast majority of analog instability issues before they ever reach the oscilloscope. For deeper mathematical modeling of phase margin and Bode plots, the All About Circuits Semiconductor Textbook remains an indispensable, free reference for bench engineers.
