Loop inductance is the total magnetic inductance of a complete current path, encompassing both the forward signal conductor and its return path. While many hobbyists and junior engineers obsess over the inductance of a single wire or trace, physics dictates that current must always return to its source. The physical area enclosed by this outbound-and-return journey creates a magnetic field, and the energy stored in that field is what we measure as loop inductance. Think of the magnetic flux lines like a rubber band wrapping around both the outbound and return wires; the further apart you pull the wires, the more the band stretches, storing more energy and increasing inductance. In modern 2026 designs featuring gigahertz-speed digital logic and nanosecond-switching wide-bandgap power semiconductors, ignoring this return path is the primary cause of ground bounce, electromagnetic interference (EMI), and catastrophic voltage spikes.
The Geometry of the Return Path
Inductance is not an intrinsic property of a single piece of copper; it is a geometric property of the entire loop. The larger the physical area between the forward conductor and the return conductor, the higher the loop inductance. This is why a single loose wire hanging in the air has a massive, poorly defined inductance, while a tightly coupled coaxial cable has a very low, highly controlled inductance.
To design reliable circuits, you must select physical geometries that minimize this loop area. The table below provides baseline loop inductance values for common conductor arrangements, assuming standard copper conductors at room temperature.
| Conductor Geometry | Physical Dimensions (Approx.) | Loop Inductance (nH/inch) | Loop Inductance (nH/cm) |
|---|---|---|---|
| PCB Microstrip (over solid ground plane) | 5 mil trace, 5 mil FR4 dielectric | ~8.0 nH/in | ~3.1 nH/cm |
| Coaxial Cable (e.g., RG-316 50Ω) | 0.5mm center, 1.6mm shield ID | ~6.5 nH/in | ~2.5 nH/cm |
| Twisted Pair (e.g., Cat6 Ethernet) | 24 AWG, 2 twists per inch | ~15.0 nH/in | ~5.9 nH/cm |
| Parallel Wires (Ribbon Cable) | 24 AWG, 0.05" (1.27mm) pitch | ~22.0 nH/in | ~8.6 nH/cm |
| Laminated Copper Busbar | 1" wide, 2 mil dielectric spacing | ~0.8 nH/in | ~0.3 nH/cm |
Notice the dramatic difference between parallel wires and a laminated busbar. By forcing the return path to sit directly adjacent to the forward path (separated only by a thin dielectric), the loop area approaches zero, effectively canceling out the magnetic fields. This principle, detailed in foundational texts like All About Circuits' guide to inductance, is the bedrock of high-speed PCB stackup design and high-power inverter busbar engineering.
Worked Example: Calculating Ground Bounce and Voltage Spikes
To understand what loop inductance changes in a real circuit, we must look at Faraday’s law of induction, specifically the voltage induced by a changing current: V = L × (di/dt). When a switch turns on or off rapidly, the rate of change of current (di/dt) is massive. Even a few nanohenries of loop inductance will generate destructive voltage spikes.
Scenario: You are designing a 48V-to-12V buck converter using a modern 100V Gallium Nitride (GaN) FET. The FET switches a 20A load in just 2 nanoseconds.
di/dt = 20A / 2ns = 10 A/ns.
Let us calculate the voltage spike across the high-frequency decoupling capacitor loop under two different layout conditions:
- Optimized Layout (2 nH loop inductance): The ceramic decoupling capacitor is placed immediately adjacent to the GaN FET, with tight, symmetrical vias to a buried ground plane.
V_spike = 2 nH × 10 A/ns = 20V
Total drain-source voltage = 48V (nominal) + 20V (spike) = 68V. The 100V GaN FET survives easily. - Poor Layout (15 nH loop inductance): The decoupling capacitor is placed 0.5 inches away, connected via long, thin traces with a wide loop area to the ground plane.
V_spike = 15 nH × 10 A/ns = 150V
Total drain-source voltage = 48V + 150V = 198V. The 100V GaN FET instantly experiences avalanche breakdown and is destroyed.
This is not a theoretical edge case; it is the most common failure mode in modern power electronics prototyping. The loop inductance of your decoupling path directly dictates whether your circuit functions or literally explodes.
Where You Meet Loop Inductance in Practice
Loop inductance is not confined to silicon and PCBs; it governs behavior across every scale of electrical work, from microprocessors to mains wiring.
1. High-Speed PCB Design
In digital logic, a signal is only as good as its return path. If a high-speed trace crosses a split in the ground plane, the return current is forced to detour around the split. This massive increase in loop area creates a localized inductor, resulting in severe signal reflections, crosstalk, and radiated EMI. Always ensure solid, unbroken reference planes beneath high-speed traces.
2. Power Electronics and Snubbers
When designing snubber circuits to tame ringing in motor drives or inverters, the physical placement of the snubber resistor and capacitor is more critical than their component values. If the snubber loop area is large, the loop inductance of the snubber itself will prevent it from absorbing the high-frequency energy, rendering the circuit useless.
3. Mains Wiring and the NEC
Loop inductance is a critical safety factor in AC mains installations. According to the National Electrical Code (NEC) Article 300.3(B), all conductors of the same circuit (hot and neutral) must be routed in the same raceway or cable. If you run the hot wire through one steel conduit and the neutral through another, you create a massive loop area. The 50/60Hz alternating magnetic field will induce severe eddy currents in the ferrous steel conduits, causing them to overheat and potentially start a fire. Keeping the conductors tightly bundled minimizes the loop area, causing the opposing magnetic fields to cancel each other out.
Common Confusions: Partial vs. Loop Inductance
The most frequent mistake engineers make is confusing partial inductance with loop inductance.
Partial inductance is a mathematical abstraction used by 3D electromagnetic field solvers (like ANSYS HFSS or Keysight ADS). It assigns an inductance value to a single segment of wire, assuming a return path at infinity. It is a useful computational intermediate, but it is physically meaningless on its own. You cannot measure partial inductance with a multimeter or an LCR meter.
Loop inductance is the physical reality. It is the sum of the partial self-inductances of the forward and return paths, minus their mutual inductance. When you place the probes of an impedance analyzer across a capacitor or a trace, you are always measuring loop inductance. If a datasheet or simulation tool quotes an inductance value without specifying the return path geometry, treat that number with extreme skepticism.
Frequently Asked Questions
Does twisting wires actually reduce loop inductance?
Twisting wires does not significantly reduce the total loop inductance compared to two straight parallel wires held at the exact same spacing. However, twisting ensures that the spacing remains constant and, more importantly, it causes external magnetic interference to couple equally into both wires as common-mode noise, which a differential receiver can easily reject.
How do I measure the loop inductance of a PCB trace?
You cannot easily measure it with a standard handheld LCR meter due to the low nanohenry values and probe lead inductance. Instead, use a Time Domain Reflectometer (TDR) or a Vector Network Analyzer (VNA) to measure the impedance of the trace, and extract the inductance from the S-parameters using the relationship Z = jωL at low frequencies.
Why do wide traces have lower inductance than narrow traces?
A wider trace reduces the partial self-inductance of the forward path because the current distributes across a broader cross-section, reducing the internal magnetic flux. More importantly, a wider trace over a ground plane increases the mutual inductance coupling to the return path, which subtracts from the total loop inductance.






