When designing digital circuits, reading logic table symbols correctly is the difference between a functional PCB and a bricked prototype. Logic symbols represent Boolean operations visually on a schematic, while truth tables define their mathematical input/output states. The two dominant global standards you will encounter are IEEE Std 91/91A (distinctive shapes, common in the US and legacy military/aerospace designs) and IEC 60617-12 (rectangular shapes, standard in EU industrial, PLC, and modern VLSI designs).
This reference provides the exact schematic symbols, Boolean expressions, and truth tables for the 7 fundamental logic gates, along with the real-world electrical characteristics that truth tables deliberately leave out.
How to Read This Logic Symbol & Truth Table Chart
Before jumping to the data, understand how the columns map to your specific installation and design environment:
- Gate / Function: The fundamental Boolean operation.
- IEEE 91A Symbol: The "distinctive shape" column. Use this if you are designing for US-based hobbyist platforms, legacy military hardware, or using standard US-centric CAD libraries (like default Altium or KiCad US libraries).
- IEC 60617-12 Symbol: The "rectangular shape" column. Use this if you are programming PLCs (IEC 61131-3), designing for European industrial markets, or working with modern microcontroller block diagrams.
- Truth Table: The binary input/output matrix.
0represents Logic LOW (GND), and1represents Logic HIGH (VCC).
Bookmark-friendly quick jumps:
The Complete Logic Table Symbols Reference Chart
The following table synthesizes data from All About Circuits' Digital Logic chapter and standard Texas Instruments Logic Portfolio datasheets.
| Gate | Boolean Expression | IEEE 91A (Distinctive) | IEC 60617-12 (Rectangular) | Truth Table (A, B → Y) |
|---|---|---|---|---|
| AND | Y = A · B | D-shaped flat back, curved front | Rectangle with & symbol inside | 0,0→0 | 0,1→0 | 1,0→0 | 1,1→1 |
| OR | Y = A + B | Curved back, pointed front (shield) | Rectangle with ≥1 symbol inside | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→1 |
| NOT | Y = A' | Triangle pointing right | Rectangle with '1' and output bubble | 0→1 | 1→0 |
| NAND | Y = (A · B)' | AND shape with output bubble | Rectangle with & and output bubble | 0,0→1 | 0,1→1 | 1,0→1 | 1,1→0 |
| NOR | Y = (A + B)' | OR shape with output bubble | Rectangle with ≥1 and output bubble | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→0 |
| XOR | Y = A ⊕ B | OR shape with extra curved back line | Rectangle with =1 symbol inside | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→0 |
| XNOR | Y = (A ⊕ B)' | XOR shape with output bubble | Rectangle with =1 and output bubble | 0,0→1 | 0,1→0 | 1,0→0 | 1,1→1 |
How Active-Low and Threshold Derating Modify Base Logic
In wire ampacity charts, derating rows modify the base current capacity based on temperature. In digital logic, active-low inputs (inversion bubbles) and voltage threshold derating modify the base truth table behavior in practice.
Active-Low Modifications (De Morgan's Equivalents)
When a logic symbol features a small circle (bubble) on an input pin, it indicates an active-low input. This physically inverts the signal before it reaches the gate's internal logic. According to De Morgan's Laws, an AND gate with active-low inputs behaves identically to a standard OR gate with an active-low output (a NOR gate). If you are reading a schematic with mixed bubbles, do not just read the base shape; trace the bubbles to determine the true logical outcome.
Voltage Threshold Derating
A truth table assumes ideal 0V and VCC states. In reality, as your supply voltage sags (e.g., a 5V rail dropping to 4.2V under load), the logic thresholds derate. For standard 5V CMOS (like the 74HC family), the minimum HIGH input voltage ($V_{IH}$) is typically $0.7 \times V_{CC}$. If VCC derates to 4.2V, your $V_{IH}$ drops to 2.94V. If your driving microcontroller is outputting a weak 2.8V HIGH due to trace resistance, the gate will read it as a logic LOW, causing the physical circuit to ignore the truth table entirely.
What the Truth Table Cannot Tell You
Logic table symbols define logical behavior, but they omit the electrical realities that dictate whether your circuit will actually work at speed. Here is what the chart above leaves out:
- Propagation Delay ($t_{pd}$): A truth table shows instantaneous state changes. In reality, a 74HC00 NAND gate has a typical propagation delay of 8ns at 5V, while a 74LS00 has about 10ns. In high-speed clock lines, these nanoseconds accumulate and cause clock skew.
- Fan-Out Limits: The table implies one output can drive infinite inputs. Physically, a standard 74HC output can source/sink about 25mA. If you connect it to ten 74LS inputs (which draw roughly 0.4mA each when LOW), you are near the limit. Exceeding fan-out causes voltage droop and logic errors.
- Metastability: If inputs to a flip-flop or latch change simultaneously (violating setup/hold times), the output may enter a metastable state—hovering between 0 and 1—before resolving. Truth tables have no symbol for "undefined oscillating voltage."
- Open-Drain vs. Push-Pull: A standard logic symbol implies a push-pull output (actively drives HIGH and LOW). If the symbol has a small diamond or specific note indicating an open-drain output (like the 74HC03), it can only pull LOW. You must provide an external pull-up resistor to achieve a Logic 1.
Frequently Asked Questions
What is the difference between IEEE and IEC logic table symbols?
The IEEE Std 91A standard uses "distinctive shapes" (e.g., a D-shape for AND, a shield shape for OR) which are highly recognizable and dominate US schematics and hobbyist platforms like Arduino. The IEC 60617-12 standard uses uniform rectangular blocks with internal text identifiers (e.g., "&" for AND, "≥1" for OR). IEC symbols are preferred in complex VLSI design and European industrial PLC programming because the rectangular blocks are easier to draw and scale in dense schematics.
How do I read an XOR logic table symbol with three inputs?
A 3-input XOR gate (often labeled with an =1 symbol inside an IEC rectangle, or a distinctive XOR shape with three input lines) outputs a Logic 1 if an odd number of inputs are HIGH. It does not output a 1 only when exactly one input is HIGH. For example, inputs 1, 1, 1 will result in a Logic 1 output (since three is an odd number). If you need a "true" 3-input XOR (where exactly one input must be high), you must build it using a combination of standard 2-input gates and an inhibit signal.
Why does my logic symbol have a triangle with a circle on the output?
A standalone triangle is the IEEE symbol for a buffer (or a NOT gate if the circle is present). A triangle with a circle on the output is an inverter (NOT gate). If the triangle is drawn with an open collector/drain symbol (a small hook or diamond at the tip), it indicates an open-drain inverter (like a 74HC04 variant), meaning it requires an external pull-up resistor on the output line to achieve a HIGH state.
Can I mix IEEE and IEC symbols in the same schematic?
While CAD software like KiCad or Altium Designer will allow you to place them on the same sheet, it is considered poor engineering practice. Mixing standards reduces schematic readability and can cause confusion during peer review or manufacturing handoff. Choose IEEE distinctive shapes for board-level component schematics, and stick to IEC rectangular blocks for FPGA/ASIC internal block diagrams or PLC ladder logic, keeping the two domains strictly separated.
