The logic symbol for OR represents a digital gate that outputs a HIGH (1) state if at least one of its inputs is HIGH. Because global engineering teams use different drafting standards, you will encounter two distinct symbol shapes on schematics: the traditional curved ANSI/IEEE shape and the rectangular IEC shape. Below is the complete reference data for identifying, drafting, and testing these gates.
Complete OR Gate Symbol & IC Reference Table
| Standard / Region | Symbol Shape | Designation / Qualifier | Common IC Part (DIP-14) | Truth Table Output (Y) |
|---|---|---|---|---|
| ANSI/IEEE Std 91 (US) | Curved D-shape with pointed back | None (Shape implies function) | SN7432 (TTL), CD4071 (CMOS) | A + B |
| IEC 60617 (Intl/EU) | Rectangle | ≥1 (Inside rectangle) | 74HC32 (High-speed CMOS) | A + B |
| MIL-STD-806 (Legacy US) | Curved D-shape | Often marked with '+' inside | 5432 (Military grade TTL) | A + B |
| 3-Input OR (Universal) | Wider D-shape or Rectangle | 3 input lines, '≥1' for IEC | 743232 / 74HC27 (Triple 3-input) | A + B + C |
Regional Standards: ANSI/IEEE vs. IEC 60617
When reading or drafting schematics, the standard you use depends on your region and the legacy of the design house. Neither is 'wrong,' but mixing them on a single schematic is considered poor drafting practice.
The ANSI/IEEE Std 91-1984 Traditional Symbol
In the United States, and in most legacy American textbooks, the logic symbol for OR is drawn as a D-shape with a curved back and a pointed front. This distinctive shape relies entirely on geometry to convey function; there are no alphanumeric qualifiers inside the gate body. If you are working with older US military schematics (MIL-STD-806) or vintage consumer electronics from the 1980s and 90s, this is the symbol you will see. It is highly recognizable but scales poorly on dense, modern VLSI block diagrams.
The IEC 60617 Rectangular Symbol
The International Electrotechnical Commission (IEC) standard 60617-12 mandates rectangular boxes for all logic gates to ensure uniform scaling and easier automated drafting. To differentiate the gates, IEC uses internal alphanumeric qualifiers. The logic symbol for OR in IEC is a rectangle containing the characters ≥1. This mathematical qualifier translates to 'the output is true if the sum of the high inputs is greater than or equal to one.' If you are working with European equipment, modern industrial PLCs, or contemporary FPGA block diagrams, the IEC rectangular standard applies to your region.
Reference Table & Truth Table Rows People Get Wrong
When interpreting the logic symbol for OR, beginners and seasoned technicians alike frequently misread specific rows in both the truth table and the symbol reference chart.
Truth Table Row: A=1, B=1, Output=1
The most common error occurs on the final row of the 2-input truth table. Because the gate is named 'OR,' many hobbyists intuitively map it to the English exclusive-or ('either A or B, but not both'). In digital logic, a standard OR gate is inclusive. If Input A is HIGH (1) and Input B is HIGH (1), the output is HIGH (1). If you need the output to be LOW when both inputs are HIGH, you are looking for the XOR (Exclusive OR) gate, which features a double-curved back in ANSI schematics.
Symbol Reference Row: The IEC '≥1' Qualifier
Technicians used to ANSI symbols often look at the IEC rectangular symbol with '≥1' inside and misinterpret the '1' as a buffer, a single-input gate, or a logic HIGH tie. The symbol must be read as a single mathematical operator: Greater Than or Equal To One. Conversely, an IEC AND gate uses the '&' symbol, and an IEC XOR uses '=1'. Confusing the '≥1' OR symbol with a standard buffer (which has no internal text in IEC, or just a '1' in some non-standard variants) will lead to catastrophic troubleshooting errors.
Safe Interpretation When Markings are Faded or Missing
On aging PCBs, the silkscreen logic symbols and IC part numbers often fade, flake off, or are obscured by conformal coating. If you cannot read the logic symbol for OR on the board, do not guess based on trace routing. Use this bench-verified multimeter and logic probe sequence to safely identify the gate type:
- Identify Power Pins: Locate Pin 14 (VCC) and Pin 7 (GND) on the 14-pin DIP IC using a multimeter in continuity mode against the board's ground plane and 5V rail.
- Power the Board: Apply nominal voltage (usually 5V for 74-series TTL/CMOS).
- Isolate a Gate: Pick pins 1, 2 (inputs) and 3 (output).
- Test the 'Both HIGH' Row: Force Pin 1 and Pin 2 HIGH. If Pin 3 goes LOW, the IC is an XOR gate (e.g., 7486). If Pin 3 stays HIGH, it is an OR gate (e.g., SN7432).
- Test the 'One HIGH' Row: Force Pin 1 HIGH and Pin 2 LOW. If Pin 3 is HIGH, you have confirmed an OR or XOR. If Pin 3 is LOW, the IC is an AND gate (e.g., 7408).
Frequently Asked Questions
What is the logic symbol for OR in ladder logic?
In PLC ladder logic, there is no graphical 'gate' symbol like you would find on an electronic schematic. The logic symbol for OR is represented by two Normally Open (NO) contact instructions placed in parallel branches. If either rung branch A or branch B is closed (TRUE), the coil on the right side of the rung energizes. This parallel routing perfectly mirrors the electrical behavior of two physical switches wired in parallel across a 24VDC control circuit.
How do you draw a 3-input logic symbol for OR?
For a 3-input OR gate, the ANSI traditional symbol is drawn with the same curved D-shape, but the back curve is elongated to accommodate a third input line entering the top, middle, and bottom of the gate. In the IEC rectangular standard, the box is simply drawn taller to fit three input lines on the left side, and the internal qualifier remains ≥1. The Boolean logic remains identical: the output is HIGH if one, two, or all three inputs are HIGH. Common ICs for this include the 74HC27 (Triple 3-Input OR).
What is the Boolean expression for the OR gate symbol?
The Boolean algebraic expression for the logic symbol for OR is written as Y = A + B (using the plus sign to denote logical addition) or Y = A ∨ B (using the logical disjunction symbol). In software programming and hardware description languages like Verilog or VHDL, it is typically written using the pipe operator Y = A | B or the keyword OR. Never use the mathematical multiplication dot or asterisk, as those denote the AND function.
