The Complete Logic Gates Truth Table & Logic Family Reference

A logic gates truth table defines the exact boolean output for every possible combination of binary inputs. While the boolean math tells you what the gate should do, building a reliable circuit requires understanding the electrical reality of the silicon executing that math. Below is the master reference for standard 2-input logic gates, followed by the critical logic family specifications, temperature derating data, and the physical limitations that a simple truth table hides.

The Master Logic Gates Truth Table

How to read this table: The A and B columns represent the binary input states (0 = Low/GND, 1 = High/VCC). The subsequent columns represent the output (Y) for each specific gate type. For single-input gates like the NOT gate (inverter), the B input is ignored. Bookmark these quick-jump rows for the most queried universal gates: NAND and XOR.

Source: Standard boolean algebra definitions as outlined in the All About Circuits Digital Logic Textbook.

Logic Family Specifications & Temperature Derating

A truth table assumes ideal, instantaneous switching. In reality, you must select a logic family that matches your microcontroller's voltage levels and environmental constraints. The table below details the electrical characteristics of common DIP and SMD logic families.

How to read this table: The V_IH (Min) column is the minimum voltage the chip guarantees to read as a '1'. The V_IL (Max) is the maximum voltage it guarantees to read as a '0'. The Temp Range column dictates the ambient operating limits. Which column applies to your installation? If you are interfacing with a 5V Arduino Uno, the 74HC or 74LS columns apply. If you are wiring a 3.3V ESP32 or Raspberry Pi, you must use the 74LVC family or run a 74HC chip at 3.3V; feeding 5V 74LS outputs into a 3.3V ESP32 GPIO will fry the microcontroller.

Source: Texas Instruments Logic Portfolio and JEDEC JESD8C CMOS standards.

How derating rows modify the base value: The propagation delay ($t_{pd}$) and output drive current listed in datasheets are baseline values measured at 25°C. As your installation approaches the upper limit of the Temp Range column (e.g., 85°C for commercial 74HC, or 125°C for military/automotive CD4000B series), the silicon's carrier mobility drops. Expect the $t_{pd}$ to increase (derate) by roughly 0.5% to 1% per °C above 25°C. Furthermore, the maximum safe sink/source current ($I_{OL}$/$I_{OH}$) derates by approximately 10-15% at maximum temperature. If you are driving a 20mA relay coil with a logic gate in a 70°C enclosure, you must check the derating curve in the specific manufacturer's datasheet to ensure the output transistor won't thermally fail.

What the Truth Table Cannot Tell You

Relying solely on a logic gates truth table leads to three common bench failures:

• Metastability: If inputs A and B change states at the exact same nanosecond (e.g., in an XOR gate transitioning from 0,1 to 1,0), the output may briefly enter an undefined voltage state between 0 and 1 before resolving. The truth table assumes static inputs; it does not warn you about setup and hold time violations.
• Propagation Hazards (Glitches): Because physical gates have propagation delays, a change in input takes nanoseconds to reach the output. In complex combinational logic, signals traveling through different numbers of gates will arrive at the final output at slightly different times, causing momentary 'glitches' or false pulses that the truth table does not predict.
• Fan-Out Limits: The truth table shows a '1' or '0', but doesn't tell you how many other gate inputs that single output can physically drive. A standard 74LS00 can only drive about 10 LS-TTL inputs (fan-out of 10) before the output voltage sags below the V_IH threshold of the receiving gates.

Logic Gates Truth Table FAQ

How do I read a 3-input logic gates truth table?

A 3-input gate (like a 74HC11 3-input AND gate) simply adds a third column (Input C) to the left side of the table. Because each input has 2 possible states, a 3-input table will have $2^3 = 8$ rows (000 through 111). For an AND gate, the output is '1' only on the very last row (1,1,1). For an OR gate, the output is '0' only on the very first row (0,0,0).

Why is the NAND logic gates truth table called a universal gate?

The NAND gate is 'universal' because you can build any other logic function (AND, OR, NOT, XOR) using only NAND gates. For example, tying both inputs of a NAND gate together creates a NOT gate (inverter). Feeding the output of a NAND gate into a NOT-gate-configured NAND gate creates an AND gate. This is why early memory and processor architectures heavily favored NAND topologies—they minimized the number of unique transistor layouts required on the silicon die.

How does a logic gates truth table change when using active-low inputs?

When a gate has active-low inputs (denoted by a 'bubble' on the schematic symbol, like the 74HC03 open-collector NAND), the physical truth table remains the same, but the logical interpretation flips. An active-low AND gate (which is physically a NOR gate) will output a '1' only when all inputs are '0'. When reading datasheets, always check if the inputs are active-high or active-low, as this completely inverts the expected control logic for enable and reset pins.

Where can I find the logic gates truth table for flip-flops and latches?

Flip-flops (like the 74HC74 D-type flip-flop) do not use standard combinational truth tables. Instead, they use characteristic tables and timing diagrams. Because their outputs depend on the previous state and the edge of a clock signal (rising or falling edge), a static truth table cannot capture their behavior. You must refer to the 'Function Table' in the specific IC's datasheet, which includes columns for Clock (↑ or ↓), Preset, Clear, and the previous state ($Q_n$).