Logic gates are the physical building blocks of digital electronics, but the symbols used to represent them on schematics vary wildly depending on whether you are looking at a US-based hobbyist schematic or a European industrial PLC diagram. Below is the direct reference for the seven fundamental logic gates, mapping their traditional shapes to modern rectangular standards and their physical silicon equivalents.
The Complete Logic Gates Symbols Reference Chart
This table maps the core logic functions to both major drafting standards, alongside the Boolean algebra and the most common modern 5V/3.3V CMOS IC part numbers you will actually buy at the bench.
| Gate Function | ANSI/IEEE Shape (US) | IEC 60617 Code (EU) | Boolean Expression | Standard 74HC IC (Quad/Dual/Hex) |
|---|---|---|---|---|
| AND | D-shape with flat input back | Rectangle with & |
Y = A · B | 74HC08 (Quad 2-Input) |
| OR | Curved shield / crescent shape | Rectangle with ≥1 |
Y = A + B | 74HC32 (Quad 2-Input) |
| NOT (Inverter) | Triangle with output bubble | Rectangle with 1 & output bubble |
Y = A' | 74HC04 (Hex Inverter) |
| NAND | D-shape with output bubble | Rectangle with & & output bubble |
Y = (A · B)' | 74HC00 (Quad 2-Input) |
| NOR | Curved shield with output bubble | Rectangle with ≥1 & output bubble |
Y = (A + B)' | 74HC02 (Quad 2-Input) |
| XOR | Curved shield with extra input curve | Rectangle with =1 |
Y = A ⊕ B | 74HC86 (Quad 2-Input) |
| XNOR | XOR shape with output bubble | Rectangle with =1 & output bubble |
Y = (A ⊕ B)' | 74HC266 (Quad 2-Input) |
The 74HC series listed above is strictly rated for 2.0V to 6.0V operation. If you are repairing older equipment that runs logic at 12V or 15V, you must use the CD4000 series (e.g., CD4011 for NAND) instead. Feeding 12V into a 74HC00 will instantly destroy the silicon junction.
Regional Standards: ANSI/IEEE vs. IEC 60617
When reading or drawing schematics, you must choose a standard based on your region and industry. Mixing them on a single schematic is a hallmark of sloppy design and leads to misinterpretation on the assembly line.
ANSI/IEEE Std 91-1984 (The "Traditional" US Standard)
Dominant in North America, hobbyist maker spaces, and US-based university programs. This standard relies on distinctive geometric shapes to convey function. You recognize an AND gate by its flat back and rounded front; an OR gate by its pointed ends and curved back. It is highly visual, making it easy to trace signal flow at a glance, but it becomes cluttered when dealing with complex programmable logic arrays.
IEC 60617-12 (The European / Industrial Standard)
Mandated in the EU and heavily used in global industrial automation (PLC ladder logic and electrical schematics). This standard uses uniform rectangular blocks. The function is defined entirely by the alphanumeric code inside the box (like & for AND, or ≥1 for OR). While it looks like a wall of identical boxes to a beginner, it scales perfectly for complex microprocessors where drawing 500 unique shapes would be impossible.
Which applies to you? If you are designing PCBs for US consumer electronics or writing tutorials for Arduino/ESP32 makers, use ANSI/IEEE. If you are drafting control panels for manufacturing or working with IEC-compliant PLCs (like Siemens S7 or Allen-Bradley), use IEC 60617.
Rows People Get Wrong (And How to Fix Them)
Even experienced engineers misread specific logic gate symbols when fatigue sets in. Here are the most common schematic traps.
- XOR vs. OR: The XOR symbol (ANSI) has a secondary, detached curved line parallel to the input side of the main shield. If that line is missing, it is a standard OR gate. In IEC, look closely at the number:
≥1means OR (output high if one or more inputs are high), while=1means XOR (output high if exactly one input is high). - De Morgan’s Equivalents (The "Bubbled OR"): A NAND gate is logically identical to an OR gate with inversion bubbles on its inputs. Schematic designers often swap the standard NAND D-shape for a "bubbled OR" shape to indicate active-low intent (e.g., a reset line). If you see an OR shape with bubbles on the inputs, do not buy an OR chip; it functions as a NAND. Buy a 74HC00.
- Inverter Bubble Placement: A bubble means logical inversion (NOT). It can be placed on the output of a gate, or the input. Electrically, a bubble on the output of an AND gate (NAND) behaves identically to bubbles on the inputs of an OR gate. Always trace the bubble to see where the signal actually flips.
Decision Tree: Identifying Faded or Missing Gate Markings
When repairing a legacy PCB, the silkscreen labeling the logic ICs is often burned off or missing. Use this decision path to identify the mystery chip and select a replacement.
| Diagnostic Step | Observation / Action | Next Step / Result |
|---|---|---|
| 1. Count the Pins | 14-pin DIP or SOIC package. | Proceed to Step 2. (If 16-pin, it's likely a 3-input gate or flip-flop). |
| 2. Identify Power Pins | Pin 14 is VCC, Pin 7 is GND. Apply 5.0V DC. | Chip draws < 2mA quiescent. Proceed to Step 3. |
| 3. Pulse Input A | Hold Input B to GND (Logic 0). Pulse Input A (Logic 0 to 1). | If Output Y stays HIGH regardless of A: It is an AND or NAND gate. Proceed to Step 4. |
| 4. Pulse Both Inputs | Apply Logic 1 to both Input A and Input B simultaneously. | If Output Y goes LOW: It is a NAND gate. |
| 5. Final Pick | You have confirmed a Quad 2-Input NAND configuration. | Buy a Texas Instruments SN74HC00N (DIP-14) or NXP 74HC00D (SOIC-14). |
Never leave CMOS logic gate inputs floating (unconnected) while testing. A floating input acts as an antenna, picking up mains hum and causing the internal transistors to oscillate rapidly. This will overheat and destroy the IC. Always tie unused inputs to VCC or GND via a 10kΩ resistor.
Safe Interpretation and Bench Testing Thresholds
When probing logic gates with a multimeter or oscilloscope, you cannot assume that anything above 2.5V is a "1" and anything below is a "0". The physical silicon interprets voltages based on strict threshold windows defined in the manufacturer datasheets (such as the Texas Instruments SN74HC00 datasheet).
For modern 74HC (High-Speed CMOS) logic running at a nominal 5.0V:
- V_IL (Maximum Low Input): 1.35V. Anything below this is guaranteed to be read as a logic 0.
- V_IH (Minimum High Input): 3.15V. Anything above this is guaranteed to be read as a logic 1.
- The Forbidden Zone: Voltages between 1.35V and 3.15V are undefined. If your multimeter reads 2.2V on an input pin, the gate is in a metastable state, likely due to a failing pull-up resistor or a slow-rising RC timing circuit.
For legacy 74LS (Low-Power Schottky TTL) logic, the thresholds are different. V_IL is 0.8V and V_IH is 2.0V. If you are replacing a 74LS00 with a 74HC00 to save power, be aware that 74HC inputs require a higher voltage to register a logic HIGH. A 3.3V microcontroller (like an ESP32) can easily drive a 74HC input, but if you are interfacing with older 5V TTL sensors that only output 2.4V for a HIGH, the 74HC chip might fail to register the signal. In that specific edge case, use a 74HCT00 (the 'T' stands for TTL-compatible thresholds), which bridges the gap between CMOS power efficiency and legacy TTL voltage levels, as detailed in standard NXP logic family documentation.
