When you are prototyping a digital interface or debugging a mixed-voltage microcontroller system, abstract Boolean algebra won't save you. You need exact voltage thresholds, propagation delays, and part numbers. This reference guide cuts through the theory and gives you the definitive lookup for logic gates circuits and truth tables, mapped directly to the physical silicon families you actually buy in 2026 (74HC, 74LVC, and legacy CD4000).
The Master Logic Gates Circuits and Truth Tables Reference
Below is the consolidated truth table for the five fundamental gates, paired with their standard quad-package IC part numbers across the three most common bench families. Standard logic thresholds follow Texas Instruments Logic Selection Guide and JEDEC JESD8 specifications.
| Gate Type | Boolean Expression | Truth Table (A, B → Y) | 74LVC (3.3V/5V Tolerant) | 74HC (5V Native) | CD4000 (Legacy Wide-V) |
|---|---|---|---|---|---|
| AND | Y = A · B | 0,0→0 | 0,1→0 1,0→0 | 1,1→1 |
SN74LVC08A | SN74HC08 | CD4081B |
| OR | Y = A + B | 0,0→0 | 0,1→1 1,0→1 | 1,1→1 |
SN74LVC32A | SN74HC32 | CD4071B |
| NAND | Y = (A · B)' | 0,0→1 | 0,1→1 1,0→1 | 1,1→0 |
SN74LVC00A | SN74HC00 | CD4011B |
| NOR | Y = (A + B)' | 0,0→1 | 0,1→0 1,0→0 | 1,1→0 |
SN74LVC02A | SN74HC02 | CD4001B |
| XOR | Y = A ⊕ B | 0,0→0 | 0,1→1 1,0→1 | 1,1→0 |
SN74LVC86A | SN74HC86 | CD4030B |
How to Read the Logic Family Specifications
Knowing the truth table is only half the battle; the physical silicon must recognize your microcontroller's voltage levels as valid logic highs and lows. When looking at a logic IC datasheet, you will see columns for VCC (Supply Voltage), VIH (Input High Voltage threshold), and VIL (Input Low Voltage threshold).
Which column applies to your installation? You must look at the VIH and VIL columns that correspond to your actual VCC operating voltage, not the absolute maximum ratings. If you are powering a 74HC08 at 5V, the VIH threshold is typically 3.15V. If you try to drive that input with a 3.3V ESP32 GPIO pin, the 3.3V signal is dangerously close to the 3.15V threshold, leaving almost zero noise margin. The gate will read it as a '1', but a 200mV ground bounce will flip it to a '0'. Conversely, if you power a 74LVC08A at 3.3V, the VIH threshold drops to 2.0V, giving your 3.3V ESP32 signal a massive 1.3V noise margin.
• The 3.3V-to-5V Translation Row: Use 74LVC powered at 3.3V. Its inputs are 5V-tolerant, meaning you can safely feed it 5V signals from an Arduino Uno without frying the chip, while it outputs clean 3.3V logic back to your ESP32.
• The High-Current Drive Row: If you need to drive a relay or an LED directly from a logic gate, look at the IOL (Output Low Current) column. Standard 74LVC sinks 24mA. If you need 50mA+, you must add a MOSFET driver or use a specialized buffer like the SN74LVC245A.
Derating Propagation Delay and Fan-Out Limits
Datasheets list a base propagation delay (tpd)—the time it takes for a change at the input to reflect at the output. However, this base value assumes a specific capacitive load (CL), usually 15pF or 50pF depending on the family. In a real PCB layout, your trace capacitance and the input capacitance of the next gates will exceed this base value, which derates your maximum operating frequency.
How derating rows modify the base value: For the 74LVC family, the typical derating factor is roughly 0.8ns per picofarad (pF) of additional load.
Worked Example: The SN74LVC08A datasheet lists a typical tpd of 4.1ns at VCC = 3.3V with CL = 50pF. If your PCB trace is long and you are driving 4 inputs of a 74HC family (each presenting ~10pF of input capacitance), your total load is 40pF (trace) + 40pF (gates) = 80pF.
Calculation: 4.1ns + ((80pF - 50pF) × 0.8ns/pF) = 4.1ns + 24ns = 28.1ns actual propagation delay.
This means your absolute maximum toggle frequency drops from ~100 MHz down to roughly 17 MHz. Always calculate the derated tpd before using logic gates in high-speed clock paths.
Decision Tree: Picking Your Exact Logic IC
Stop guessing which silicon to drop in your cart. Follow this decision path to terminate on a specific, purchasable part number for your next logic gates circuits and truth tables implementation.
| System Condition (If...) | Requirement (Then...) | Concrete Part Number Pick |
|---|---|---|
| Microcontroller is 3.3V (ESP32/Pico) AND you need to interface with 5V sensors. | 3.3V VCC operation with 5V-tolerant inputs. | SN74LVC08A (Quad AND) or SN74LVC245A (Octal Buffer) |
| System is strictly 5V (Arduino Uno/Mega) AND you need standard speed. | 5V VCC operation, high noise immunity. | SN74HC08 (Quad AND) or SN74HC14 (Hex Schmitt-Trigger) |
| You only need ONE gate to save board space, not a full quad package. | Single-gate micro-package (SOT-23 or SOT-553). | SN74LVC1G08 (Single AND) or SN74LVC1G04 (Single NOT) |
| Operating from a raw battery (3V to 9V) AND speed is under 1 MHz. | Wide supply voltage range (3V to 15V). | CD4081B (Quad AND) or CD4093B (Quad NAND Schmitt) |
| Input signals are noisy, slow-moving, or analog ramps (e.g., LDR sensor). | Schmitt-trigger inputs to prevent output oscillation. | SN74LVC14 (Hex Inverter) or SN74HC132 (Quad NAND) |
Default Recommendation: If your project uses a modern 3.3V microcontroller and you have no specific high-voltage or ultra-low-speed constraints, standardize your bench inventory on the 74LVC-A series (e.g., SN74LVC08A). It covers 90% of modern hobbyist and prototyping logic translation needs.
What the Specification Table Cannot Tell You
While the JEDEC and manufacturer tables give you static DC thresholds and idealized AC timing, they omit critical physical layout realities. According to advanced digital design principles outlined in All About Circuits Digital Electronics, relying solely on the logic table will lead to failures in three specific scenarios:
- Simultaneous Switching Noise (SSN): If all four outputs of a 74HC08 flip from HIGH to LOW at the exact same nanosecond, the sudden rush of current through the ground pin inductance causes 'ground bounce'. The chip's internal ground reference spikes above the PCB ground, potentially registering as a false logic HIGH on the inputs. The table doesn't warn you about this; you must mitigate it by placing a 100nF ceramic decoupling capacitor as physically close to the VCC/GND pins as possible.
- Parasitic Oscillation in Unconnected Inputs: CMOS logic gates (all 74xx and CD40xx families) have extremely high input impedance. The table assumes inputs are driven. If you leave an input pin floating, it will act as an antenna, pick up RF noise, and cause the gate to oscillate at high frequencies, destroying your power budget through internal heating. Always tie unused inputs to VCC or GND with a 10kΩ resistor.
- ESD Sensitivity on the Bench: The 74LVC family is highly optimized for low capacitance and fast switching, making it exceptionally sensitive to Electrostatic Discharge. While the datasheet might claim 2kV HBM (Human Body Model) protection, walking across a carpeted workshop in winter and touching an unpowered 74LVC chip will easily punch through the input protection diodes. Handle them in anti-static bags until the moment they go into the breadboard or solder mask.
