If you are designing a digital circuit, debugging a state machine, or just trying to figure out why your 74-series chip is outputting garbage, you need a reliable logic gates chart. A proper reference chart doesn't just show you the Boolean truth tables; it maps those logical operations to physical integrated circuits (ICs), defines their voltage thresholds, and outlines their timing constraints.

Below is the master reference chart for standard 2-input logic gates, followed by the critical IC family specifications you need to select the right chip for your bench project or PCB layout.

The Master Logic Gates Chart (Truth Tables & IC Mapping)

This table maps the fundamental Boolean operations to their standard truth tables, IEEE/IEC symbols, and the most common physical IC part numbers. The symbols follow the IEEE 91-1984 / IEC 60617 standards, while the IC part numbers adhere to JEDEC naming conventions for standard logic families.

How to read this table: The 'Inputs' and 'Outputs' columns use standard positive logic (1 = HIGH, 0 = LOW). The 'Standard IC' columns give you the exact part number prefix for the two most common logic families (CMOS and TTL). Use the anchor links below to jump to the specific gate you are troubleshooting.
Gate Type Boolean Expression Inputs (A, B) to Output (Y) CMOS IC (74HC Series) TTL IC (74LS Series)
AND Y = A · B 0,0→0 | 0,1→0 | 1,0→0 | 1,1→1 74HC08 74LS08
NAND Y = ~(A · B) 0,0→1 | 0,1→1 | 1,0→1 | 1,1→0 74HC00 74LS00
OR Y = A + B 0,0→0 | 0,1→1 | 1,0→1 | 1,1→1 74HC32 74LS32
NOR Y = ~(A + B) 0,0→1 | 0,1→0 | 1,0→0 | 1,1→0 74HC02 74LS02
XOR Y = A ⊕ B 0,0→0 | 0,1→1 | 1,0→1 | 1,1→0 74HC86 74LS86
NOT (Inverter) Y = ~A 0→1 | 1→0 (Single Input) 74HC04 74LS04

Source: Truth tables derived from standard Boolean algebra; IC mappings per JEDEC standard logic nomenclature. For deeper symbol geometry, refer to the All About Circuits Digital Textbook.

Selecting Your Logic Family: Which Column Applies to You?

Looking at the chart above, you have to choose between CMOS (74HC) and TTL (74LS). Which column applies to your installation depends entirely on your power supply voltage and your speed requirements. Mixing these families without level-shifting is a classic bench mistake that leads to undefined logic states.

Specification 74HC (High-Speed CMOS) 74LS (Low-Power Schottky TTL) 4000 Series (Standard CMOS)
Supply Voltage (VCC) 2.0V to 6.0V 4.75V to 5.25V (Strict 5V) 3.0V to 15.0V
Input Threshold Proportional to VCC (~50%) Fixed (~1.4V) Proportional to VCC (~50%)
Typical Propagation Delay ~8 ns (at 5V) ~9 ns ~50 ns (at 5V)
Static Power Draw Nanoamps (Extremely low) Milliamps (Moderate) Nanoamps (Extremely low)
Best Use Case Battery-powered, 3.3V/5V mixed Legacy 5V bus interfacing High-voltage (9V/12V) systems

The Verdict: Choose 74HC for 95% of modern hobbyist and prototype designs. It runs happily off 3xAA batteries (4.5V) or a standard 5V USB supply, and interfaces reasonably well with 3.3V microcontrollers if you use HCT variants (74HCT) for TTL-compatible input thresholds. Choose 74LS only if you are repairing vintage 1980s computer gear or need to interface with older 5V-only bus architectures. For detailed electrical characteristics, always check the specific manufacturer's datasheet, such as the Texas Instruments SN74HC00 datasheet.

Propagation Delay, Fan-Out, and Loading Deratings

In wire sizing, derating adjusts ampacity based on temperature and conduit fill. In digital logic, derating modifies the base propagation delay ($t_{pd}$) and fan-out based on capacitive loading. The logic gates chart gives you the 'ideal' truth table, but physics dictates how fast that truth table can execute.

How Capacitive Load Derates Timing

Every logic gate output has a finite drive strength, typically capable of sourcing or sinking 4mA to 8mA. Every gate input, plus the physical PCB trace or breadboard wire connecting them, adds parasitic capacitance ($C_L$).

  • Base Value: A 74HC00 NAND gate has a typical $t_{pd}$ of 8ns at 5V with a 15pF load.
  • The Derating Factor: If you route a long trace or hang 10 gate inputs on a single output, your load capacitance might climb to 50pF.
  • The Result: The propagation delay derates (increases) by roughly 0.5ns per additional picofarad. Your 8ns delay just became 25ns. In a high-speed clock circuit, this skew will cause setup/hold time violations and crash your state machine.

Fan-Out Limits

Fan-out is the number of standard inputs a single output can reliably drive.

Bench Rule of Thumb: A single 74HC output can safely drive up to 10 other 74HC inputs (Fan-out = 10). However, if you are driving a heavy load like an LED or a relay coil, you must use a buffer (like the 74HC244) or a transistor. Never source more than 25mA absolute maximum from a single 74HC VCC/GND pin, and keep individual I/O pin current under 6mA to avoid voltage droop.

What the Logic Gates Chart Cannot Tell You

A truth table assumes perfect components and instantaneous transitions. Real-world silicon has edge cases that will ruin your day if you ignore them. Here is what the chart leaves out, and how to protect your circuit against them.

1. Floating Inputs Cause Oscillation and Overheating

The chart assumes inputs are firmly at a logic 1 or 0. In reality, CMOS inputs (74HC and 4000 series) have incredibly high impedance. If you leave an input pin unconnected (floating), it acts as an antenna, picking up ambient electromagnetic noise. The internal MOSFETs will rapidly toggle back and forth between HIGH and LOW, causing the IC to draw massive current and overheat. Fix: Always tie unused CMOS inputs to VCC or GND using a 10kΩ pull-up/pull-down resistor.

2. Ground Bounce and VCC Sag

When multiple outputs on a 74LS or 74HC chip switch from HIGH to LOW simultaneously, the sudden rush of current through the inductance of the chip's ground pin causes a momentary voltage spike on the internal ground plane. This 'ground bounce' can trick adjacent inputs into reading a false HIGH. Fix: Place a 100nF (0.1µF) ceramic decoupling capacitor as physically close to the VCC and GND pins of every single logic IC as possible. Do not share decoupling caps across multiple chips.

3. Metastability in Asynchronous Signals

If an input signal changes state at the exact nanosecond the gate is evaluating its output (violating setup and hold times), the gate can enter a 'metastable' state—outputting a voltage halfway between 0 and 1, or oscillating wildly for several nanoseconds before settling. Truth tables don't have a row for 'maybe'. Fix: Never feed raw, asynchronous external signals (like a mechanical switch or an external sensor) directly into a clocked logic array. Always pass them through a hardware debouncer or a dual D-flip-flop synchronizer chain first.