The Complete Logic Gate Truth Table Reference: TTL, CMOS, and Boolean Basics

A logic gate truth table maps every possible combination of binary inputs to a single binary output for a specific Boolean function. If you are designing a digital circuit, debugging a state machine, or interfacing microcontrollers with discrete logic, the truth table is your foundational blueprint. However, a theoretical table of 1s and 0s only tells half the story. To actually build reliable hardware, you must map those abstract states to real-world voltage thresholds, propagation delays, and logic family specifications.

The Master Logic Gate Truth Table Reference

How to read this table: The table below outlines the standard 2-input logic gates. The Inputs (A, B) columns represent the binary states (0 = LOW, 1 = HIGH) applied to the physical IC pins. The Output (Y) column shows the resulting steady-state Boolean response. The symbols referenced align with the IEEE Std 91-1984 / IEC 60617 standard for rectangular logic symbols. Bookmark the quick-jump rows for the most frequently queried gates in digital design: NAND, NOR, and XOR.

Voltage Thresholds: Which Logic Family Column Applies?

A truth table assumes ideal 0s and 1s, but physical silicon operates on analog voltage thresholds. The most critical mistake hobbyists make is assuming a "HIGH" is exactly 5.0V. To determine which column applies to your installation, you must identify your logic family (TTL vs. CMOS) and your supply voltage ($V_{CC}$).

The table below defines the guaranteed input and output voltage thresholds based on the Texas Instruments Logic Guide (SDYA009) specifications, measured at a standard 25°C ambient temperature.

Timing Derating: How Real-World Factors Modify the Base Table

The base truth table implies instantaneous state changes. In reality, derating rows modify the base value by introducing propagation delay ($t_{pd}$) and limiting fan-out based on capacitive loading and temperature. Just as wire ampacity is derated for heat, logic gate switching speed is derated for capacitive load.

If you drive a 74HC00 NAND gate with a heavy capacitive load (e.g., a long coaxial cable or multiple parallel gate inputs), the output rise/fall times degrade. Here is how capacitive loading derates the propagation delay of a standard 74HC00 at 5V:

• 15 pF load: $t_{pd}$ ≈ 8 ns (Base datasheet value)
• 50 pF load: $t_{pd}$ ≈ 15 ns (Typical breadboard/short trace)
• 100 pF load: $t_{pd}$ ≈ 28 ns (Long traces or high fan-out)

Furthermore, temperature derating affects your voltage thresholds. As ambient temperature rises from 25°C to 85°C, the $V_{IH}$ (minimum HIGH input) for CMOS drops slightly, while the leakage current increases. If you are designing for an industrial enclosure that hits 60°C, you must add a 10-15% noise margin buffer to your $V_{IH}$ calculations to prevent false triggering.

What the Truth Table Cannot Tell You

A truth table is a steady-state Boolean map. It is entirely blind to the physical realities of silicon. Here is what the table hides:

1. Floating Inputs: The table assumes inputs are tied to a solid 0 or 1. If you leave an input pin unconnected on a CD4011 (CMOS), it acts as an antenna. It will pick up EMI, oscillate rapidly between states, and cause internal "shoot-through" current that can overheat and destroy the IC or rapidly drain a battery.
2. Metastability: If inputs A and B on a flip-flop or latch change state at the exact same picosecond (violating setup/hold times), the output may enter a metastable state—hovering between 0 and 1 for an unpredictable duration before resolving. Truth tables do not account for timing violations.
3. Current Sourcing vs. Sinking: The table tells you the output will be "1". It does not tell you that a standard 74LS00 can sink 16mA to ground (LOW state) but can only source a pathetic 0.4mA to $V_{CC}$ (HIGH state). If you try to drive an LED directly from a TTL HIGH output, it will barely glow.

Logic Gate Truth Table FAQ

How do I read a 3-input logic gate truth table?

A 3-input gate (like a 74HC10 triple 3-input NAND) simply adds a third column to the input matrix. Because each input has 2 possible states, a 3-input table will have $2^3 = 8$ rows. You read it exactly like the 2-input table: trace the specific combination of A, B, and C across the row to find the resulting Y output. For a 3-input AND gate, the output is only HIGH (1) on the very last row where A=1, B=1, and C=1.

Why does my CMOS logic gate output random values when an input is disconnected?

CMOS gates (like the 4000 series or 74HC series) have exceptionally high input impedance (often >$10^{12}$ ohms). A disconnected pin does not default to LOW; it floats. It will capacitively couple to nearby signals, mains hum, or static electricity, causing the internal MOSFETs to switch erratically. Always tie unused CMOS inputs to either $V_{CC}$ or GND using a direct wire or a 10kΩ pull-up/pull-down resistor.

Can I mix 74LS TTL and 74HC CMOS gates in the same 5V circuit?

Yes, but with a critical caveat regarding the truth table voltage thresholds. A 74LS TTL output HIGH ($V_{OH}$) is guaranteed to be at least 2.7V. However, a 74HC CMOS input requires a minimum HIGH ($V_{IH}$) of 3.5V. If you drive a 74HC input directly from a 74LS output, the CMOS gate might interpret the 2.7V TTL HIGH as an undefined state. To fix this, add a 4.7kΩ pull-up resistor from the TTL output to the 5V $V_{CC}$ rail to boost the voltage above the 3.5V CMOS threshold.

What is the practical difference between an XOR and an XNOR truth table?

The XOR (Exclusive OR) truth table outputs a 1 only when the inputs are different (0,1 or 1,0). It is fundamentally a "difference detector" and is used in binary adders and parity generators. The XNOR truth table is the exact inverse; it outputs a 1 only when the inputs are the same (0,0 or 1,1). XNOR gates are used as "equivalence detectors" in digital comparators and error-checking circuits.