The symbol of logic gates you draw on a schematic or read on a datasheet depends entirely on your regional standard. In the US and among hobbyists, the ANSI/IEEE 91 standard uses distinctive geometric shapes (a curved D for AND, a curved shield for OR). In Europe and industrial PLC programming, the IEC 60617 standard uses uniform rectangular boxes with internal alphanumeric codes (& for AND, ≥1 for OR). If you are ordering physical parts, you will be hunting for 74-series or 4000-series ICs based on these logical functions.
The Master Logic Gate Symbol & IC Reference Table
Use this table to translate between schematic symbols, boolean math, and the physical silicon you need to buy. The part numbers listed are the industry-standard quad/dual configurations in 14-pin DIP or SOIC packages.
| Gate Function | ANSI/IEEE 91 Shape | IEC 60617 Code | Boolean Expression | Common 5V IC (74HC) | Common 3.3V IC (74LVC) |
|---|---|---|---|---|---|
| Buffer | Triangle pointing right | 1 | Y = A | 74HC125 (Quad, 3-state) | 74LVC125 |
| NOT (Inverter) | Triangle with output bubble | 1 (with overline or negation symbol) | Y = A' | 74HC04 (Hex) | 74LVC04 |
| AND | Flat back, curved D front | & | Y = A · B | 74HC08 (Quad) | 74LVC08 |
| OR | Curved back, pointed shield front | ≥1 | Y = A + B | 74HC32 (Quad) | 74LVC32 |
| NAND | AND shape with output bubble | & (with output negation) | Y = (A · B)' | 74HC00 (Quad) | 74LVC00 |
| NOR | OR shape with output bubble | ≥1 (with output negation) | Y = (A + B)' | 74HC02 (Quad) | 74LVC02 |
| XOR | OR shape with extra curved input line | =1 | Y = A ⊕ B | 74HC86 (Quad) | 74LVC86 |
| XNOR | XOR shape with output bubble | =1 (with output negation) | Y = (A ⊕ B)' | 74HC266 (Quad) | 74LVC266 |
Regional Standards: Which Symbol Set Applies to You?
Choosing the right symbol set prevents miscommunication when sharing schematics or reading legacy documentation.
- ANSI/IEEE Std 91-1984: The undisputed king of the workbench. It relies on shape recognition. You instantly know it's an OR gate because of the curved back and pointed front. Most EDA tools (KiCad, Altium, EasyEDA) default to these libraries in US regions.
- IEC 60617-12: The international standard. Every gate is a rectangle. You must read the text inside to know the function. An AND gate is a box with an '&' symbol. This standard scales much better for complex, custom programmable logic arrays where drawing a unique shape for a 64-input AND gate would be impossible.
- Legacy MIL-STD-806 & DIN 40700: You will only see these on schematics from the 1970s and 80s. DIN used half-arrows for NAND/NOR. Ignore these for new designs, but know how to read them if you are repairing vintage synthesizers or old military radio gear.
The 'Rows People Get Wrong' Notes
When reading a schematic under poor lighting or tracing a complex bus, these specific symbol variations cause the most bench-debugging headaches.
1. XOR vs. XNOR (The Tail Bubble)
The XOR symbol features a secondary curved line spaced slightly away from the main input curve. The XNOR adds an inversion bubble to the output. However, some older CAD libraries place the inversion bubble on the input side of that secondary curve. Both are logically identical, but if you are hand-tracing a PCB, ensure you aren't misreading an XNOR as a standard XOR with a disconnected trace.
2. De Morgan's Equivalents (NAND drawn as Negative-OR)
A NAND gate (AND shape with output bubble) is logically identical to an OR gate with bubbles on its inputs (Negative-OR). Schematic designers often use the Negative-OR symbol to clarify intent—specifically when dealing with active-low signals. If you see an OR shape with input bubbles, do not go looking for a specialized IC; just grab a standard 74HC00 NAND gate.
3. The Schmitt Trigger Hysteresis Loop
If you see a standard buffer or inverter triangle with a small 'squiggly line' (resembling a resistor symbol or a hysteresis loop) inside the body, it is a Schmitt Trigger. This is not a standard logic gate; it has two different threshold voltages to clean up noisy, slow-rising analog signals into crisp digital squares. You must buy a Schmitt-specific IC like the 74HC14 (Hex Inverter), not a standard 74HC04.
Decision Path: Selecting Your Standard and Silicon
Use this decision matrix to terminate your design choices into a concrete bill of materials.
| Design Scenario | Schematic Standard | Concrete IC Family Pick | Why This Pick? |
|---|---|---|---|
| 5V Arduino / Breadboard prototyping | ANSI/IEEE 91 | 74HC series (e.g., 74HC08) | Wide 2V-6V operating range, high noise immunity, cheap DIP availability. |
| 3.3V ESP32 / Raspberry Pi GPIO interfacing | ANSI/IEEE 91 | 74LVC series (e.g., 74LVC08) | Operates down to 1.65V, 5V-tolerant inputs on many pins, fast propagation. |
| Harsh industrial / 12V-15V automotive logic | IEC 60617 | CD4000B series (e.g., CD4011) | Handles up to 18V VCC, extremely robust against voltage spikes, slower speed. |
| High-speed memory bus / RF mixing | ANSI/IEEE 91 | 74AUC / 74AVC | Sub-nanosecond propagation delays, tiny BGA/micro-QFN packages. |
Bench Rescue: Identifying Faded or Unmarked Logic ICs
When you are salvaging parts from a donor board and the laser etching on a 14-pin DIP is faded or missing, you can safely identify the logic gate using a multimeter and a 5V bench supply. According to Texas Instruments' logic design guidelines, standardizing your testing approach prevents shorting the die.
- Establish Power Rails: On 95% of standard 14-pin DIP logic ICs (both 74HC and CD4000 series), Pin 14 is VCC and Pin 7 is GND. Apply 5V to Pin 14 and ground Pin 7. (Note: 74HC02 NOR and 74HC04 Hex Inverter have different internal pin mappings, but VCC/GND remain on 14/7).
- Map the Inputs and Outputs: Gates are usually grouped. For a quad 2-input gate, Pins 1 & 2 are inputs, and Pin 3 is the output. Pins 4 & 5 are inputs, Pin 6 is output. Pin 11 is the final output.
- Build the Truth Table: Set your multimeter to DC Voltage. Ground both inputs (Pins 1 & 2). Measure the output (Pin 3).
- If Output is HIGH (~5V) → It's a NAND or NOR.
- If Output is LOW (~0V) → It's an AND or OR.
- The Tie-Breaker: Pull one input HIGH (5V) and leave the other LOW (GND).
- If the output flips HIGH, it's an OR (or NOR, if it flipped LOW). You now know it's an OR/NOR family.
- If the output stays the same, it's an AND/NAND family.
By systematically applying 5V and GND to the input pins and logging the output voltage, you can definitively identify any unmarked basic logic gate in under two minutes without relying on faded silkscreen. For complex 3-state buffers or flip-flops, consult the specific NXP or TI logic family datasheets to map the enable and clock pins before applying power.
