A logic gate mux (multiplexer) is a digital switch that routes one of several input signals to a single output line based on the binary state of its select pins. In physical circuit design, a mux changes the board layout by drastically reducing the number of microcontroller GPIO pins and PCB traces required to monitor multiple sensors or route data buses. Think of it like a railroad switch yard: multiple incoming tracks (inputs) converge, but the switch operator (select pins) dictates exactly which single track connects to the main outbound line (output).
The Core Mechanism: Selecting Inputs with Binary Math
To understand the internal logic, we will look at the industry-standard 74HC151, an 8-channel digital multiplexer. It features eight data inputs (D0 through D7), three select lines (S0, S1, S2), one normal output (Y), one inverted output (W), and an active-low Enable pin (E).
When the Enable pin is pulled LOW (active), the mux decodes the binary value present on the select pins to determine which input connects to the output. Let us walk through a concrete numeric example.
Worked Numeric Example: Routing Input D5
- Target: You want the signal at Input D5 to appear at Output Y.
- Binary Conversion: The decimal number 5 translates to binary
101. - Pin States: You must drive the select pins to match this binary value from most significant to least significant: S2 = 1 (HIGH), S1 = 0 (LOW), S0 = 1 (HIGH).
- Internal Action: The internal AND/OR gate matrix decodes the
101state. It closes the CMOS transmission gate for D5 while keeping the gates for D0-D4 and D6-D7 in a high-impedance (blocking) state. - Outcome: If D5 is sitting at 4.8V, Output Y will read 4.8V (minus a negligible internal millivolt drop typical of CMOS logic).
Where You Meet a Logic Gate Mux in Practice
You will rarely use a standalone logic gate mux in simple LED blinker projects, but they become indispensable as system complexity scales. Here are the three most common applications on the bench:
- GPIO Expansion for Sensor Arrays: If you need to read 16 DIP switches for a hardware configuration menu, routing them directly to a microcontroller wastes 16 pins. By using two cascaded 8-channel muxes, you can read all 16 switches using just 5 GPIO pins (3 shared select lines + 2 data output lines).
- I2C Bus Routing: Many popular sensors, like the BME280 environmental sensor, have hardcoded I2C addresses (e.g.,
0x76). If you need eight BME280s on one Arduino, you cannot wire them to the same SDA/SCL lines. An I2C multiplexer (like the TCA9548A, which is essentially an I2C-controlled bank of logic gate muxes) routes the master bus to one sensor at a time. - Analog Signal Multiplexing: While the 74HC151 is strictly for digital logic, its analog cousin, the CD4051, uses similar select-pin logic to route analog voltages. This allows a microcontroller with a single ADC pin to read eight different thermistor voltage dividers sequentially.
Bench Walkthrough: Debugging a 74HC151 Multiplexer Circuit
Theory is clean; the workbench is messy. Here is a real-world scenario demonstrating how a logic gate mux behaves when voltage thresholds are mismatched.
The Setup
I was building a diagnostic tool to read 8 digital limit switches on a CNC router using an ESP32 DevKit v1 and a Texas Instruments SN74HC151N. The ESP32 operates at 3.3V logic, but the limit switches and the 74HC151 were powered from the machine's 5.0V rail. I wired the ESP32 GPIOs directly to the S0, S1, and S2 select pins.
The Numbers and Outcome
With 10kΩ pull-up resistors on all 8 switch inputs, I wrote a loop to cycle through binary states 000 to 111. Switches 0 through 3 triggered cleanly. The serial monitor showed perfect HIGH/LOW transitions when the physical switches were toggled.
What Went Wrong
When testing switches 4 through 7, the output fluttered wildly between HIGH and LOW, even when the switch was held firmly closed. The routing was failing on the upper half of the mux.
The Root Cause: I had ignored the $V_{IH}$ (High-level input voltage) threshold in the TI SN74HC151 datasheet. For a 5V-powered HC-family chip, the minimum voltage guaranteed to register as a logic HIGH on the select pins is $0.7 \times V_{CC}$, which equals 3.5V. The ESP32 was only outputting 3.3V.
Select states 0-3 only require S0 or S1 to go HIGH, and the 3.3V signal barely scraped by the threshold due to silicon variance. However, states 4-7 require S2 to be HIGH. The 3.3V signal on S2 fell into the undefined linear region of the input buffer, causing the internal logic to oscillate and randomly route noise instead of the D4-D7 inputs.
The Fix
Swapping the 74HC151 for a 74LVC151 (which accepts 3.3V inputs as a valid HIGH even when VCC is 5V) or adding a BSS138 bidirectional level shifter on the select lines instantly fixed the erratic routing.
Common Confusions: Mux vs. Demux vs. Encoder
Because these ICs all feature similar pin counts and deal with binary conversion, they are frequently mixed up in component ordering. According to the All About Circuits multiplexer guide, the distinction lies entirely in data flow direction and purpose.
| Component | Data Flow | Primary Function | Common Part Number |
|---|---|---|---|
| Multiplexer (Mux) | Many-to-One | Routes one specific input to a single output line. | 74HC151 |
| Demultiplexer (Demux) | One-to-Many | Routes a single input to one of many output lines. | 74HC138 |
| Encoder | Many-to-One | Compresses multiple active lines into a binary code (does not route arbitrary data). | 74HC147 |
| Decoder | One-to-Many | Converts a binary code into a single active output line (often used for driving displays). | 74HC42 |
FAQ: Logic Gate Mux Edge Cases and Timing
What happens to the output when I change select pins?
When you change the select pins, the mux undergoes a break-before-make transition. The old input is disconnected before the new input is connected. This creates a brief high-impedance state at the output, which can cause a momentary voltage glitch if the output line has high parasitic capacitance. Always allow a few nanoseconds for the output to settle after toggling select lines before reading the data pin.
How much propagation delay does a logic gate mux add?
Propagation delay ($t_{pd}$) is the time it takes for a change at the input to appear at the output. For a standard 74HC151 operating at 5V, $t_{pd}$ is typically around 18 nanoseconds. While this is irrelevant for reading mechanical switches, it becomes a critical bottleneck if you are trying to multiplex a 20 MHz SPI clock signal. For high-speed buses, you must use specialized low-capacitance bus muxes like the TS3DS10224.
Can I leave unused mux inputs floating?
Never leave CMOS inputs floating. A floating input acts as an antenna, picking up electromagnetic interference and causing the internal transistors to rapidly switch states. This leads to excessive current draw and thermal runaway. Always tie unused data inputs to either VCC or GND via a 10kΩ resistor, or directly if the IC datasheet permits.
