Designing LDO Stability: How Equivalent Series Resistance ESR of Capacitors Dictates Loop Compensation

The LDO Output Topology and the ESR Zero

The equivalent series resistance (ESR) of capacitors is the parasitic internal resistance that appears in series with an ideal capacitance. While power supply designers often treat ESR as a loss mechanism to be minimized, in Low-Dropout Regulator (LDO) design, ESR is a critical compensation component. It creates a zero in the feedback control loop that prevents the regulator from oscillating under load.

Consider the standard small-signal topology of an externally compensated LDO. The output network consists of the LDO pass element driving Node A ($V_{OUT}$). From Node A, current flows through the capacitor's parasitic resistance ($R_{ESR}$) to Node B ($V_{CAP}$), and finally through the ideal capacitance ($C_{OUT}$) to Node C (GND). The LDO's feedback pin samples Node A. The interaction between $R_{ESR}$ and $C_{OUT}$ creates a zero at the frequency $f_z = 1 / (2\pi \times R_{ESR} \times C_{OUT})$. This zero provides the necessary phase boost to maintain a stable loop margin.

Real-World Capacitor ESR Data and Selection

You cannot design a stable compensation network using nominal capacitance alone; you must design around the specific ESR at the LDO's crossover frequency (typically 100kHz to 1MHz). Below is a data-dense comparison of real-world components you will encounter on the bench.

Design Walkthrough: Compensating an LM1117-3.3

Let's design the output filter for a classic TI LM1117-3.3 LDO supplying 500mA to a mixed-signal microcontroller. The TI Power House design guides and the LM1117 datasheet explicitly demand an output capacitor $\ge$ 22µF with an ESR strictly between 0.1Ω and 1.0Ω.

If you grab three Murata 10µF X5R MLCCs and parallel them to get 30µF, your total capacitance is sufficient, but your parallel ESR drops to roughly 1mΩ. The ESR zero moves to 5MHz, far beyond the LDO's unity-gain bandwidth. The phase margin collapses, and the LDO will oscillate. To fix this using MLCCs, you must add a discrete 0.22Ω 0805 resistor in series with the capacitor bank. Alternatively, a single Panasonic EEU-FR1E101 (100µF, 0.24Ω ESR) satisfies both the capacitance and ESR requirements natively, requiring no extra discrete components.

Behavior Matrix: What Changes When ESR Shifts

ESR is not a static value. It varies with temperature, frequency, and age. Understanding how the circuit behaves as ESR drifts is critical for robust design.

Failure Modes at the Extremes: Open vs. Short

To truly understand the equivalent series resistance of capacitors in circuit design, you must analyze what happens when the topology breaks down at its mathematical extremes.

The "Shorted" ESR Extreme (MLCC Bank)

When ESR is effectively shorted—such as when a designer places a massive bank of parallel MLCCs on the output without a series resistor—the ESR zero moves to infinity. The LDO's internal poles dominate the transfer function without any phase boost. The pass transistor toggles fully on and off, acting like a relaxation oscillator. You will measure a 50mV to 200mV AC ripple riding on your DC output, which can easily couple into sensitive ADC inputs or trigger false resets on brownout-detector circuits.

The "Open" ESR Extreme (Dry Cap or Broken Trace)

When ESR is effectively open (due to a failed capacitor, a broken PCB trace, or a capacitor drying out to an ESR of >10Ω), the local charge storage is severed from the high-frequency AC path. According to fundamental capacitor theory, the immediate voltage step during a load transient is dictated entirely by ESR ($\Delta V_{ESR} = \Delta I_{load} \times R_{ESR}$). If the capacitor is open, the LDO pass element must supply the entire transient current instantly. Because the LDO's control loop bandwidth is limited (usually <1MHz), it cannot react fast enough to a 300mA WiFi TX burst. The output voltage sags deeply, causing a system brownout.

Breadboard-Testing ESR and Loop Stability Step-by-Step

You do not need a $15,000 network analyzer to verify LDO stability and ESR behavior. You can extract the effective ESR and verify loop stability on the bench using a standard oscilloscope and a transient load injector.

1. Build the Circuit: Assemble your LDO (e.g., LM1117) on a breadboard. Keep the leads from the output pin to the capacitor as short as possible to minimize parasitic trace inductance, which can mask the ESR step.
2. Inject a Transient Load: Wire an N-channel MOSFET (like a 2N7000) in series with a 10Ω power resistor to ground. Drive the MOSFET gate with a function generator outputting a 1kHz square wave (0V to 5V). This creates a repetitive 330mA load step.
3. Probe Correctly: Do not use the standard 6-inch ground clip on your oscilloscope probe; the loop area will pick up switching noise. Use a tip-and-barrel (spring ground) adapter directly across the capacitor terminals. Set the scope to AC+DC coupling with a 20MHz bandwidth limit.
4. Analyze the Waveform: When the MOSFET turns on, you will see an immediate, vertical voltage drop before the capacitor begins to slew. This vertical step is $\Delta V_{ESR}$.
5. Calculate ESR: Measure the amplitude of that initial vertical step. Divide it by your known load step current ($\Delta I$). For example, if the immediate step is 66mV and your load step is 330mA, your effective circuit ESR is exactly 0.20Ω ($0.066V / 0.33A$).
6. Verify Phase Margin: Observe the ringing immediately following the ESR step. If the waveform rings more than twice before settling, your ESR is too low (phase margin is poor). Add a 0.1Ω series resistor and re-test until the response is critically damped (one minor overshoot, then flat).

By treating the equivalent series resistance of capacitors as a deliberate design parameter rather than an accidental parasitic, you ensure your power delivery network remains stable across temperature extremes, component aging, and aggressive load transients.