The fundamental LC circuit formula for resonant frequency is fr = 1 / (2π√LC). At this exact frequency, the inductive reactance (XL) and capacitive reactance (XC) are equal in magnitude but exactly 180 degrees out of phase, effectively canceling each other out. Whether you are designing an RF bandpass filter, a switching power supply snubber, or a simple crystal radio tuner, selecting the correct inductor (L) and capacitor (C) values dictates whether your circuit passes, blocks, or stores energy at your target frequency.
The Core LC Circuit Formula and Topology Nodes
To design effectively, you must map the physical topology to your schematic nodes. In a standard two-terminal LC network, we define three critical nodes:
- Node A (Input/Source): Where the AC signal or DC bias enters the network.
- Node B (Junction): The physical connection point between the inductor and the capacitor.
- Node C (Ground/Return): The common reference point or output load connection.
The resonant frequency formula relies on two underlying reactance equations that scale in opposite directions as frequency increases:
- Inductive Reactance: XL = 2πfL (Increases with frequency)
- Capacitive Reactance: XC = 1 / (2πfC) (Decreases with frequency)
At resonance, XL = XC. Setting them equal and solving for f yields the master LC circuit formula: fr = 1 / (2π√LC). However, how you arrange L and C between Nodes A, B, and C completely changes the circuit's impedance profile at that resonant frequency.
Component Behavior and Failure Modes at the Extremes
Before choosing a topology, you must understand how component tolerances, parasitics, and catastrophic failures alter the network. The table below maps element variations and extreme failure modes to their real-world bench consequences.
| Parameter Change / Failure | Effect on fr | Effect on Q-Factor | Real-World Consequence & Failure Mode |
|---|---|---|---|
| Increase L or C | Decreases | Varies | Filter passband shifts lower; may cause overlap with adjacent channels in RF IF stages. |
| Decrease L or C | Increases | Varies | Passband shifts higher; in power supplies, this can push resonance into switching noise harmonics. |
| Inductor Shorts (Wire fault) | Resonance lost | Drops to ~0 | Circuit becomes a pure capacitive load. In a parallel tank, this shorts the AC source to ground, likely blowing the driving transistor or fuse. |
| Capacitor Opens (Cracked MLCC) | Resonance lost | Drops to ~0 | DC path remains through inductor, but AC resonance ceases. In an oscillator, the circuit simply stops ringing (dead output). |
| Capacitor Shorts (Dielectric breakdown) | Resonance lost | Drops to ~0 | Inductor is placed directly across the AC source. Massive current spike; inductor will overheat and burn out unless current-limited. |
Note on parasitics: Real inductors possess parasitic parallel capacitance (winding capacitance), creating a Self-Resonant Frequency (SRF). If your target fr approaches the inductor's SRF, the component stops behaving as an inductor and becomes a capacitor, breaking the LC circuit formula entirely.
Series vs. Parallel LC: Why Choose One Topology Over the Other?
The decision between series and parallel topologies hinges entirely on what you want the circuit to do at the resonant frequency. Series resonance minimizes impedance, while parallel resonance maximizes it.
| Criteria | Series LC Topology | Parallel LC (Tank) Topology |
|---|---|---|
| Impedance at fr | Minimum (ideally zero, practically limited by ESR/winding resistance) | Maximum (ideally infinite, practically limited by parallel leakage) |
| Current at fr | Maximum (draws heavy current from source) | Minimum from source; internal circulating current between L and C is maximum |
| Primary Use Case | Bandpass filters, notch filters (when placed as a shunt to ground), impedance matching | Oscillators, IF transformers, bandstop filters, RF amplifiers (as collector/drain load) |
| Failure Risk | High current at resonance can saturate the inductor core if source impedance is too low | High circulating currents can overheat components despite low source current; high voltage spikes across nodes |
Choose Series when: You need to pass a specific frequency to a load with minimal insertion loss, or when you need to short a specific interfering frequency to ground (notch filter).
Choose Parallel when: You need to build an oscillator, create a high-impedance load for an RF amplifier to maximize voltage gain at a specific frequency, or store energy in a resonant tank.
Design Walkthrough: Tuning a 10.7 MHz FM IF Filter
Let's apply the LC circuit formula to a real-world scenario: designing a parallel resonant tank for a 10.7 MHz FM Intermediate Frequency (IF) stage. This is a standard frequency in FM radio architecture.
Step 1: Fix one variable based on physical constraints.
At 10.7 MHz, stray breadboard capacitance and PCB pad capacitance typically add 2pF to 5pF. If we choose a tiny capacitor (e.g., 10pF), parasitics will dominate and detune the circuit. If we choose a massive capacitor (e.g., 10nF), the required inductor becomes impractically small and lossy. A 100pF capacitor is the sweet spot for VHF/UHF IF stages.
Step 2: Calculate the required Inductance.
Rearranging the LC circuit formula to solve for L:
L = 1 / [ (2πfr)² × C ]
L = 1 / [ (2 × π × 10.7 × 10⁶)² × (100 × 10⁻¹²) ]
L = 1 / [ 4.519 × 10¹⁵ × 100 × 10⁻¹² ]
L = 1 / 451,900 ≈ 2.21 µH
Step 3: Select real-world components.
We need standard E12/E24 values with high stability. For the capacitor, a C0G/NP0 ceramic dielectric is mandatory; X7R or Y5V dielectrics exhibit severe capacitance drift with temperature and applied DC bias, which will pull your 10.7 MHz frequency off-target. For the inductor, we need a high Self-Resonant Frequency (SRF) well above 10.7 MHz to ensure it acts purely inductive.
| Component | Selected Part Number | Key Specifications | Reasoning |
|---|---|---|---|
| Capacitor (100pF) | Murata GJM1555C1H101J | 100pF, 50V, C0G/NP0, 0402 package, ±5% tolerance | C0G dielectric ensures 0ppm/°C drift; tight tolerance keeps fr accurate. |
| Inductor (2.2µH) | Coilcraft 1812CS-222X | 2.2µH, SRF = 115 MHz, Q = 50 at 7.9 MHz | SRF of 115 MHz is >10x our target frequency, preventing parasitic capacitive behavior. Coilcraft's finder confirms low AC winding losses. |
Step-by-Step Breadboard Testing and Verification
Testing an RF LC circuit on a solderless breadboard introduces massive parasitic variables. A standard breadboard row has roughly 2pF to 4pF of stray capacitance. More critically, your measurement equipment will load the circuit. A standard 1x oscilloscope probe adds ~100pF of capacitance to Node B. If you probe our 100pF tank with a 1x probe, you instantly double the capacitance, dropping the resonant frequency from 10.7 MHz down to 7.5 MHz. Always use a 10x probe (which adds only ~10pF to 15pF) and mathematically compensate for it during verification.
Follow this numbered procedure to verify your design:
- De-energize and Assemble: Ensure the signal generator is off. Insert the Coilcraft inductor and Murata capacitor into the breadboard, sharing a single 5-hole node strip (Node B). Keep lead lengths as close to zero as possible; do not use jumper wires for the LC junction.
- Connect the Source: Connect the signal generator output (set to 50Ω impedance mode, 1Vpp sine wave) to Node A via a short BNC-to-minigrabber cable. Connect the ground clip to Node C.
- Probe the Junction: Attach a 10x oscilloscope probe to Node B. Ensure the probe's compensation capacitor is trimmed using the scope's calibrator square wave before connecting to the circuit.
- Perform a Coarse Frequency Sweep: Set the signal generator to sweep from 5 MHz to 15 MHz. Observe the amplitude on the oscilloscope. For a parallel tank acting as a load, you will see a voltage peak. For a series pass configuration, you will see a peak across the load resistor.
- Identify the Peak and Compensate: Note the frequency of maximum amplitude. If it reads 10.2 MHz instead of 10.7 MHz, this is expected. The 10x probe added ~12pF, and the breadboard added ~3pF, making your total C ≈ 115pF. Verification Math: fmeasured = 1 / (2π√(2.2µH × 115pF)) ≈ 10.0 MHz. If your measured peak aligns with this adjusted calculation, your components are correct and the physical layout is behaving predictably.
- Measure the -3dB Bandwidth: Drop the signal generator amplitude to 70.7% (-3dB) of the peak voltage. Note the lower and upper frequencies where this occurs. Subtract the lower from the upper to find the Bandwidth (BW). Calculate the practical Q-factor: Q = fr / BW. A Q between 30 and 60 is typical for this component tier on a breadboard.
By anchoring your design in the exact LC circuit formula, selecting components based on parasitic realities (SRF and dielectric type), and accounting for probe loading during verification, you bridge the gap between textbook theory and functional bench hardware.
