How to Label the Parallel Vector Diagram for AC Power Factor Correction

When you label the parallel vector diagram for an AC circuit, the supply voltage (V) is always your horizontal reference phasor at 0°. Unlike series circuits where current is the common reference, parallel branches share the same voltage. Therefore, resistive current ($I_R$) is drawn in-phase (0°), inductive current ($I_L$) lags by 90° (downward), and capacitive current ($I_C$) leads by 90° (upward). The total line current ($I_T$) is the vector sum of these branch currents. This guide walks through the exact topology, failure modes, and a real-world power factor correction design to lock in these concepts.

The Core Rule: How to Label the Parallel Vector Diagram

In a parallel AC topology, the circuit splits into distinct branches between two primary nodes: Node A (Line/Hot) and Node B (Neutral/Return). Because every branch connects directly across Node A and Node B, the voltage drop is identical for all components. This makes voltage the universal reference point for your phasor diagram.

To correctly label the parallel vector diagram, follow this sequence:

1. Draw the Voltage Vector ($V$): Draw a horizontal arrow pointing right along the 0° axis. Label it $V_{source}$.
2. Draw the Resistive Current ($I_R$): Draw an arrow overlapping the voltage vector (0°). Label it $I_R$.
3. Draw the Inductive Current ($I_L$): Draw an arrow pointing straight down (-90°). Label it $I_L$. (Remember: current lags voltage in an inductor).
4. Draw the Capacitive Current ($I_C$): Draw an arrow pointing straight up (+90°). Label it $I_C$. (Current leads voltage in a capacitor).
5. Sum the Reactive Currents: Subtract the smaller reactive vector from the larger one to find the net reactive current ($I_X$).
6. Draw Total Current ($I_T$): Use the Pythagorean theorem ($I_T = \sqrt{I_R^2 + I_X^2}$) to draw the resultant vector from the origin to the tip of the net reactive current.

Behavior Matrix: What Happens When Component Values Shift

Understanding how the vector diagram morphs when you tweak a component is critical for tuning filters and compensation networks. Here is the behavior matrix for a standard parallel RLC circuit:

Design Walkthrough: Sizing a Parallel Capacitor for an RL Load

Let’s apply the vector diagram to a real-world problem: correcting the power factor of an industrial AC contactor coil. Poor power factor causes excessive line current and voltage drop.

The Load: A 120VAC, 60Hz shaded-pole motor/contactor coil drawing 0.5A at a power factor (PF) of 0.4 lagging.

1. Calculate Apparent and Real Power:
   Apparent Power ($S$) = $120V \times 0.5A = 60 VA$.
   Real Power ($P$) = $S \times PF = 60 \times 0.4 = 24 W$.
2. Calculate Existing Reactive Power ($Q_L$):
   $Q_L = \sqrt{S^2 - P^2} = \sqrt{60^2 - 24^2} = \sqrt{3600 - 576} = 55 VAR$ (lagging).
3. Define Target Power Factor:
   We want a PF of 0.95. The new phase angle $\theta = \arccos(0.95) = 18.19°$.
   Target Reactive Power ($Q_{new}$) = $P \times \tan(18.19°) = 24 \times 0.3287 = 7.89 VAR$.
4. Calculate Required Capacitor Reactive Power ($Q_C$):
   $Q_C = Q_L - Q_{new} = 55 - 7.89 = 47.11 VAR$.
5. Find Capacitance Value:
   Capacitive Reactance ($X_C$) = $V^2 / Q_C = 120^2 / 47.11 = 305.6 \Omega$.
   $C = 1 / (2 \pi f X_C) = 1 / (2 \times \pi \times 60 \times 305.6) = 8.68 \mu F$.

The Concrete Pick: Round up to a standard 10 µF motor-run capacitor rated for at least 250VAC (e.g., a Cornell Dubilier 947D series or equivalent metallized polypropylene film capacitor). Do not use electrolytic capacitors for continuous AC line compensation; they will overheat and vent.

Failure Modes: Open and Short Extremes in Parallel Topologies

When designing parallel compensation, you must account for component failure. The vector diagram collapses differently depending on the fault.

• Shorted Capacitor: If the parallel compensation capacitor fails short, it creates a dead short directly across Node A and Node B. The line current spikes to thousands of amps instantly. Result: The branch breaker trips or the fuse blows, protecting the wiring but killing power to the entire parallel bank.
• Open Capacitor: If the capacitor fails open (common in aged film caps), the $I_C$ vector disappears from your diagram. The total current $I_T$ reverts to the original lagging $I_L$ vector. Result: The system continues to run, but the power factor drops back to 0.4, causing thermal stress on the upstream wiring and potential utility penalty fees.
• Shorted Inductor (Load): A shorted primary load draws massive current, tripping the breaker. The parallel capacitor survives but loses its AC voltage source.
• Open Inductor (Load): The primary load stops functioning. The capacitor remains energized across the line, drawing a small leading current ($I_C$) that slightly raises the local node voltage due to the Ferranti effect on long feeder lines.

Contrast this with a series topology: an open component kills the entire circuit, but a shorted component simply bypasses itself, allowing the rest of the string to continue operating (albeit with altered voltage division).

Breadboard Testing: Verifying the Phase Angle Step-by-Step

Do not test parallel AC compensation directly on 120V mains on an open breadboard. Step the voltage down to safely verify your vector math using a dual-channel oscilloscope.

1. Step Down the Source: Use a 120V-to-12VAC wall transformer (60Hz). This provides a safe, isolated 12VAC reference.
2. Scale the Components: Since voltage is scaled by 10x, impedance must be scaled to maintain the same phase angle. Use a 120Ω resistor and a 47mH inductor to simulate the RL load, and a 100µF non-polarized film capacitor for compensation.
3. Insert a Shunt Resistor: Place a 10Ω, 1% non-inductive shunt resistor in the main line (between the transformer and the parallel node). This converts the total line current into a measurable voltage signal.
4. Probe Channel 1 (Voltage Reference): Connect the scope's Ch1 probe across the 12VAC transformer output. Set the trigger to Ch1 rising edge at 0V. This is your 0° reference vector.
5. Probe Channel 2 (Total Current): Connect Ch2 across the 10Ω shunt resistor. The voltage waveform here perfectly mirrors the total line current ($I_T$) waveform.
6. Measure the Shift: Use the scope's cursor function to measure the time delay ($\Delta t$) between the Ch1 zero-crossing and the Ch2 zero-crossing. Calculate the phase angle: $\theta = (\Delta t / 16.67ms) \times 360°$. If your math is correct, adding the parallel capacitor will shrink $\Delta t$ closer to zero.

Decision Tree: Choosing Your Parallel Compensation Strategy

When faced with a lagging power factor or a resonant filtering requirement, use this decision path to select the right parallel topology and component class.

The Default Recommendation: For 90% of hobbyist, bench, and standard building RL loads under 500W, the correct pick is a fixed metallized polypropylene film capacitor (like the Cornell Dubilier 947D or Illinois Capacitor PMR series) rated at 1.5x the nominal line voltage. They offer self-healing properties if a dielectric puncture occurs, preventing the catastrophic short-circuit failure mode that plagues cheaper electrolytic or ceramic alternatives in parallel AC line applications.

By correctly labeling the parallel vector diagram and mapping your branch currents to physical component values, you move from guessing capacitor sizes to engineering precise, reliable AC networks. For deeper mathematical proofs on parallel phasor addition, refer to standard references like Electronics Tutorials on Parallel RLC Circuits or the All About Circuits AC textbook.