A series circuit governed by Kirchhoff's Voltage Law (KVL) dictates that the directed sum of all electrical potential differences around a closed loop must equal zero. In practical DC design, this means your source voltage is exactly equal to the sum of the voltage drops across your series components. When you need to scale a 14.4V lead-acid battery signal down to a safe 3.0V logic level for an ESP32 analog-to-digital converter (ADC), a two-resistor series voltage divider is the most reliable, lowest-cost topology available. This guide walks through the exact math, component selection, and failure modes required to build this KVL series circuit on a breadboard.

The Core Topology: KVL in a Two-Resistor Series Loop

To apply Kirchhoff's Voltage Law to a scaling circuit, we define three specific nodes in the loop:

  • Node A ($V_{IN}$): The high-side input connected to the voltage source (e.g., a 12V nominal battery that peaks at 14.4V when charging).
  • Node B ($V_{OUT}$): The junction between the two series resistors, which routes to the microcontroller ADC pin.
  • Node C ($GND$): The low-side return path connected to the common ground plane.

Tracing the loop from Node C, up through the source, and back down through the resistors, the KVL equation is:

$V_{IN} - V_{R1} - V_{R2} = 0$

Because the components are in series, the current ($I$) is identical through both R1 and R2. The voltage drop across each resistor is simply $I \times R$. The voltage at Node B (relative to Node C) is the voltage drop across R2 alone. This yields the standard voltage divider formula: $V_{OUT} = V_{IN} \times [R2 / (R1 + R2)]$.

Bench Tip: KVL assumes ideal wires with zero resistance. On a standard solderless breadboard, contact resistance can add 0.5Ω to 2Ω per junction. For milliamp-level currents in a high-impedance divider, this introduces negligible error. For high-current series loops (like LED strings), breadboard contact resistance will cause measurable voltage drops and localized heating.

Decision Path: Why Series Over Parallel or Active Regulation?

Why use a passive series resistor topology instead of a parallel Zener diode or an active buck converter? The choice depends entirely on your current requirements and precision needs. A series KVL divider is strictly a voltage sensing topology, not a power delivery topology.

Topology Selection Decision Matrix
Condition / Requirement Recommended Topology Why This Wins
Scaling voltage for an ADC input (Load current < 1mA) Series Resistor Divider (KVL) Lowest cost, zero switching noise, linear response, minimal board space.
Clamping a signal line to protect a GPIO from transients Parallel Zener / TVS Diode Only conducts when voltage exceeds the breakdown threshold; doesn't waste power at nominal voltages.
Powering a 3.3V sensor from a 12V rail (Load current > 10mA) Active Buck Converter (e.g., LM2596) Series resistors would dissipate massive heat ($P=I^2R$) and suffer severe voltage sag under dynamic loads.
Driving a string of 3V LEDs from a 12V source Series LEDs + 1 Current-Limiting Resistor KVL ensures the resistor drops the exact remainder voltage, stabilizing current across the series LED string.

The Default Pick: For reading a battery voltage with an ESP32, the series KVL divider is the undisputed winner. It draws virtually zero quiescent current and introduces no high-frequency switching noise into your analog readings.

Design Walkthrough: 14.4V to 3.0V ESP32 Battery Monitor

Let's design the exact component values for a sealed lead-acid (SLA) battery monitor. The ESP32 ADC is nominally 3.3V, but the Espressif ESP32 Datasheet recommends keeping analog inputs below 3.1V to avoid non-linearity at the top end of the SAR ADC range. We will target a maximum of 3.0V at Node B when the battery is at its absolute peak charging voltage of 14.4V.

1. Calculate the Resistor Ratio

We need the ratio of R2 to the total resistance to be $3.0V / 14.4V = 0.2083$.

Let's anchor R2 to a standard 10kΩ value to keep the impedance low enough for the ADC, but high enough to minimize parasitic battery drain.

$0.2083 = 10k / (R1 + 10k)$
$R1 + 10k = 48,000Ω$
$R1 = 38,000Ω$ (38kΩ)

2. Select Standard E24 Component Values

38kΩ is not a standard E24 resistor value. The closest standard value is 39kΩ. Let's recalculate the actual maximum voltage with R1 = 39kΩ and R2 = 10kΩ:

$V_{OUT(max)} = 14.4V \times [10k / (39k + 10k)] = 14.4V \times (10 / 49) = 2.938V$

This is perfect. It sits safely below the 3.1V linear limit of the ESP32, leaving a 0.36V safety margin.

3. Verify Power Dissipation

Total series resistance is 49kΩ. At 14.4V, the loop current is $I = 14.4 / 49,000 = 0.294mA$.
Power dissipated by R1: $P = I^2 \times R = (0.000294)^2 \times 39,000 = 3.36mW.
A standard 1/4W (250mW) or 1/8W (125mW) through-hole resistor will run completely cool.

ADC Impedance Warning: The ESP32 uses a Successive Approximation Register (SAR) ADC. When the internal multiplexer connects the sampling capacitor (~10pF) to the GPIO pin, it draws a brief current spike. The Thevenin equivalent resistance of our 39k/10k divider is roughly 7.9kΩ. This is low enough to charge the sampling cap within the acquisition window, but adding a 100nF bypass capacitor at Node B to GND is mandatory to supply instantaneous charge and prevent artificially low readings.

Failure Mode Contrast: What Breaks at the Extremes?

Understanding how a KVL series circuit fails compared to a parallel circuit is critical for troubleshooting. In a parallel topology, if one branch opens, the other branches continue to operate normally. In a series loop, the current path is singular; a single fault alters the entire loop's behavior.

Series Circuit Failure Mode Behavior (14.4V Source)
Fault Condition Node B Voltage ($V_{OUT}$) Physical Result & Diagnostic
R1 Opens (Broken trace / lifted pad) 0.0V (Floating/Zero) Current stops. Node B is pulled to GND via R2. Multimeter reads 0V. ESP32 reads 0.
R1 Shorts (Solder bridge across R1) 14.4V (Full Source) KVL loop resistance drops to just R2. 14.4V hits the ESP32 GPIO, likely destroying the silicon.
R2 Opens (Broken resistor) 14.4V (Pulled High) No current flows to ground. Node B floats up to $V_{IN}$ through R1. ESP32 GPIO is overvolted.
R2 Shorts (Solder bridge to GND) 0.0V All source voltage drops across R1. Node B is hard-tied to GND. High current flows through R1 (370mA), risking thermal damage to R1.
Load Added (e.g., 10kΩ sensor at Node B) Drops to ~2.1V The load acts as a parallel resistor to R2, altering the equivalent resistance and breaking the original KVL ratio.

The Takeaway: An open R1 fails safe (reads 0V). An open R2 or shorted R1 fails destructive (overvolts the microcontroller). Always route your series divider traces so that a physical scratch or lifted pad is more likely to cause an open on the high-side (R1) rather than the low-side (R2).

Step-by-Step Breadboard Verification

Do not connect this circuit to your ESP32 until you have verified the KVL math on the bench. Follow this exact sequence using a digital multimeter (DMM).

  1. Insert Components: Place the 39kΩ resistor (R1) and 10kΩ resistor (R2) in series on the breadboard. Ensure they share a common junction row (Node B).
  2. Add Bypass Cap: Insert a 100nF (0.1µF) ceramic capacitor between Node B and the ground rail. This stabilizes the node against ambient RF noise.
  3. Dead Test (Resistance): With no power applied, set your DMM to resistance mode. Place the red probe on Node B and the black probe on the ground rail. You should read exactly 10.0kΩ (±1%). If you read 39kΩ, your breadboard contacts are failing to bridge R2 to ground.
  4. Apply Source: Connect a bench power supply set to 12.0V to Node A (positive) and the ground rail (negative).
  5. Verify KVL Drops: Set the DMM to DC Voltage. Measure across R1 (Node A to Node B). It should read ~9.55V. Measure across R2 (Node B to GND). It should read ~2.45V. The sum must equal your source voltage (9.55 + 2.45 = 12.0V).
  6. Simulate Peak Voltage: Raise the bench supply to 14.4V. Measure Node B to GND. It must read 2.93V to 2.95V (accounting for 1% resistor tolerance). If it reads above 3.1V, double-check your resistor color bands; you may have accidentally grabbed a 3.9kΩ instead of a 39kΩ.
  7. Connect to Microcontroller: Only after verifying the 14.4V peak test, connect Node B to your ESP32 GPIO (e.g., GPIO 34, which is input-only and lacks internal pull-ups that would skew the reading).

Final Component Selection & Implementation Default

When building this KVL series circuit for permanent deployment, carbon composition or generic 5% carbon film resistors are unacceptable. Their values drift with temperature and humidity, which will ruin your ADC calibration over time.

The Concrete Pick: Use Vishay MRS25 series 1% metal film resistors (or equivalent Yageo MF1/4W 1%). They offer a temperature coefficient of ±50ppm/°C, meaning a 30°C rise in ambient enclosure temperature will shift your 39kΩ resistor by less than 60Ω—an error entirely invisible to the 12-bit ESP32 ADC.

Final BOM for the Voltage Scaling Loop:

  • R1: 39kΩ, 1/4W, 1% Metal Film (Vishay MRS25000C3909FCT00)
  • R2: 10kΩ, 1/4W, 1% Metal Film (Vishay MRS25000C1002FCT00)
  • C1: 100nF (0.1µF), 50V, X7R Ceramic Capacitor (Murata or KEMET)

By strictly adhering to Kirchhoff's Voltage Law and selecting precision components, you transform a basic textbook topology into a robust, production-ready sensor interface. For deeper reading on passive scaling networks, refer to the SparkFun Voltage Divider Tutorial for additional load-effect calculations.