While MOSFETs dominate modern power switching, the junction field effect transistor (JFET) remains unmatched in 2026 for low-noise audio front-ends, high-impedance sensor buffering, and RF oscillators. Unlike a BJT, which is current-controlled, a JFET is a voltage-controlled device where the gate voltage physically "pinches off" the conductive channel between the drain and source. If you are designing a low-noise preamp or repairing vintage test equipment, you need to know how to select, bias, and test these components without relying on abstract physics textbooks.
This guide gives you the exact default part numbers, the math for self-biasing a common-source amplifier, and the bench tricks for testing a JFET with a standard digital multimeter (DMM).
JFET Pinout, Symbol, and Safe Default Part Numbers
Before you solder anything, you need to identify the pins and select the right silicon for the job. In the standard TO-92 package (flat side facing you, pins pointing down), the typical pinout for most US-registered JFETs like the 2N5457 or J310 is Gate (G), Source (S), Drain (D). However, always verify with the specific manufacturer's datasheet, as European PRO Electron parts (like the BF245) often use a Drain-Source-Gate arrangement.
On a schematic, the JFET symbol features a circle (sometimes omitted) with a vertical channel line and three terminals. The Gate terminal has an arrow. Mnemonic: If the arrow points IN, it's an N-channel JFET. If it points OUT, it's a P-channel. (N-channel = Not pointing out).
When you need a JFET for a prototype, don't waste time hunting down obscure parts. Here are the safe, widely available default JFETs you should keep in your bench drawer, complete with their critical datasheet limits.
| Part Number | Channel | Typical Use Case | Vds (Max) | Idss Range | Vgs(off) Range | Pd (Max) |
|---|---|---|---|---|---|---|
| J310 | N | RF amplifiers, VHF oscillators | 25V | 24mA - 60mA | -2V to -6V | 310mW |
| 2N5457 | N | Audio preamps, general switching | 25V | 1.0mA - 5.0mA | -0.5V to -6V | 310mW |
| PN4117 | N | Low-current switches, multiplexers | 25V | 0.25mA - 1.2mA | -1.0V to -4.0V | 350mW |
| J174 | P | P-channel audio, current sources | -30V | -20mA to -60mA | +2V to +6V | 350mW |
Operation Regions and Biasing the Junction Field Effect Transistor
To use a JFET as an amplifier, you must bias it in the Saturation (Active) Region. This is where the drain current (Id) is relatively constant and controlled almost entirely by the gate-to-source voltage (Vgs), making it an excellent transconductance amplifier. Here is how the device behaves across its operating regions.
| Region | Vgs Condition | Vds Condition | Behavior & Application |
|---|---|---|---|
| Cutoff | Vgs ≤ Vgs(off) | Any | Channel is fully pinched off. Id ≈ 0. (Switch OFF state). |
| Ohmic (Linear) | Vgs > Vgs(off) | Vds < (Vgs - Vgs(off)) | JFET acts as a voltage-controlled resistor. Used in analog switches and AGC circuits. |
| Saturation (Active) | Vgs > Vgs(off) | Vds ≥ (Vgs - Vgs(off)) | Channel is pinched at the drain end. Id is constant for a given Vgs. (Amplifier state). |
| Breakdown | Any | Vds > Vds(br) | Avalanche breakdown occurs. Destructive if current is not limited. |
The Math: Self-Biasing a Common-Source Amplifier
The most reliable way to bias a JFET is using a self-bias network. Because an N-channel JFET requires a negative Vgs relative to the source to operate in the active region, we place a resistor (Rs) between the source and ground. The drain current flowing through Rs creates a positive voltage at the source. Since the gate is tied to ground via a high-value resistor (Rg), the gate remains at 0V, making Vgs inherently negative.
Let's design a self-biased audio preamp using the 2N5457 (Typical Idss = 3.0mA, Typical Vgs(off) = -2.0V) with a 15V supply (Vdd). We want to bias the drain current (Id) at roughly half of Idss (1.5mA) to allow maximum symmetrical voltage swing.
Using the Shockley equation: Id = Idss * (1 - (Vgs / Vgs(off)))^2
1.5mA = 3.0mA * (1 - (Vgs / -2.0V))^2
Solving for Vgs yields approximately -0.59V.
Since Vgs = -Id * Rs, we calculate Rs:
Rs = 0.59V / 1.5mA = 393Ω. We will use the standard 390Ω resistor.
Complete Application Circuit: Low-Noise Audio Preamp
Here is the complete, buildable netlist for a common-source JFET preamp. This circuit provides high input impedance and low noise, ideal for buffering piezo pickups or condenser microphones.
- Q1: 2N5457 (N-Channel JFET)
- Rd (Drain Resistor): 5.6kΩ (Sets voltage gain; Av ≈ -gm * Rd)
- Rs (Source Resistor): 390Ω (Sets DC bias point)
- Rg (Gate Resistor): 1MΩ (Provides DC ground path for gate, sets input impedance)
- C_in (Input Coupling): 1μF film capacitor (Blocks DC from source)
- C_out (Output Coupling): 10μF film capacitor (Blocks DC from next stage)
- Cs (Source Bypass): 100μF electrolytic (Bypasses Rs for AC signals, restoring full voltage gain)
- Vdd: 12V to 15V DC regulated supply
For deeper theoretical background on the Shockley equation and transconductance curves, refer to the JFET amplifier guide on Electronics Tutorials or the Georgia State University HyperPhysics FET module.
How JFETs Fail and How to Test Them with a Multimeter
JFETs are remarkably rugged, but they have one massive Achilles' heel: Electrostatic Discharge (ESD). The gate forms a PN junction with the channel. If a static spike exceeds the reverse breakdown voltage of this junction (typically 25V to 30V), the gate junction avalanches. Unlike a MOSFET's insulated gate which might melt and short, a JFET gate junction often degrades, resulting in excessive gate leakage current. This causes the bias point to drift wildly as the gate accumulates charge.
Thermal runaway is rare in JFETs because they have a negative temperature coefficient at high currents (they self-limit), but a shorted drain-source path will still destroy the silicon if the power supply can deliver enough current to exceed the 310mW TO-92 limit.
Step-by-Step JFET Testing with a DMM
You don't need a curve tracer to verify a JFET on the bench. Grab your digital multimeter and follow these exact steps. (Note: These steps assume an N-channel JFET. For P-channel, reverse the probe polarities).
- Test the Gate-Source and Gate-Drain PN Junctions: Set your DMM to Diode Test mode. Place the red probe on the Gate and the black probe on the Source. You should read a forward voltage drop between 0.500V and 0.750V. Reverse the probes (black on Gate, red on Source); the meter should read OL (Over Limit). Repeat this process between the Gate and Drain. If you read a short (0.00V) or if the junction reads forward-biased in both directions, the JFET is dead.
- Test Drain-Source Resistance (The Bench Trick): Switch your DMM to Resistance (Ω) mode. Place probes on Drain and Source. Because the gate is floating, ambient static charge might be pinching off the channel, causing the meter to read OL or a randomly high number. Fix: Use a jumper wire (or your finger) to short the Gate to the Source. This forces Vgs = 0V, turning the JFET fully ON. The meter should now read a low resistance, typically between 100Ω and 1kΩ (this is the Rds(on) at Idss).
- Test the Pinch-Off Effect: Keep the DMM in resistance mode across Drain and Source. Remove the Gate-Source short. Now, use a jumper wire to connect the Gate to the Drain (or apply a negative voltage relative to the source if your meter supports it). On many DMMs, the internal test voltage is enough to partially bias the gate, or simply touching the gate with your finger to induce 50/60Hz mains hum will cause the resistance reading to fluctuate wildly, proving the channel is modulating. If the resistance stays locked at a low value regardless of gate manipulation, the channel is shorted.
By understanding the physical PN junction of the gate and using the Shockley equation to set your source resistor, you can reliably integrate the junction field effect transistor into modern low-noise and high-impedance designs without guessing.
