An instrumentation op amp circuit isolates and amplifies low-level differential signals riding on high common-mode voltages. Unlike a basic difference amplifier, a true instrumentation amplifier provides ultra-high input impedance and exceptional Common-Mode Rejection Ratio (CMRR). For bench prototyping and custom sensor interfaces, building a discrete three-amplifier topology using precision dual op-amps gives you complete control over gain distribution, bandwidth, and noise filtering.

This guide walks through the exact node topology, selects real 0.1% tolerance component values for targeted gains, and maps out the exact failure modes you will encounter when a resistor drifts or a solder joint goes cold.

The Three-Amplifier Topology and Node Labels

The classic discrete instrumentation amplifier relies on three operational amplifiers divided into two distinct stages. Stage 1 handles differential gain and impedance buffering, while Stage 2 handles common-mode subtraction and single-ended conversion.

  • Inputs: V_IN+ and V_IN- connect directly to the non-inverting inputs of U1A and U2A.
  • Stage 1 (Buffers & Differential Gain): U1A and U2A are configured as non-inverting amplifiers. Their inverting inputs are tied together through the gain-setting resistor, R_G. Feedback resistors R_F1 and R_F2 connect from the outputs of U1A and U2A back to their respective inverting inputs.
  • Intermediate Nodes: Node A is the output of U1A. Node B is the output of U2A. These nodes carry the amplified differential signal plus the original common-mode voltage.
  • Stage 2 (Difference Amplifier): U3 is configured as a standard difference amplifier. Node A feeds into U3's inverting input via R_3. Node B feeds into U3's non-inverting input via R_5. Feedback resistor R_4 bridges U3's output and inverting input, while R_6 ties U3's non-inverting input to ground.
  • Output: V_OUT is taken from the output pin of U3.
Bench Tip: Always place 100nF ceramic decoupling capacitors as physically close to the VCC and VEE pins of U1, U2, and U3 as possible. High-impedance sensor nodes will easily rectify RF interference if the power rails are noisy, destroying your CMRR.

Component Selection and Gain Behavior

When designing an instrumentation op amp circuit, you must distribute the gain between Stage 1 and Stage 2. Pushing all the gain into Stage 1 maximizes CMRR because the differential signal is amplified before the subtraction stage, meaning any common-mode errors introduced by Stage 2 resistor mismatches are divided by the Stage 1 gain.

For this design walkthrough, we will fix Stage 2 as a unity-gain subtractor (R_3 = R_4 = R_5 = R_6 = 10.0 kΩ, 0.1% thin-film). We will set Stage 1 feedback resistors to R_F1 = R_F2 = 49.9 kΩ (0.1%). The overall gain formula simplifies to:

G = 1 + (2 × 49.9kΩ) / R_G = 1 + (99.8kΩ / R_G)

Below is the design table for standard target gains using readily available 0.1% tolerance metal film resistors (e.g., Susumu RG or Vishay Z-Foil series). We also calculate the required op-amp slew rate to maintain a clean 10 kHz signal at full output swing (assuming a ±10V output limit).

Target Gain (G) R_G Value (0.1%) Actual Calculated Gain Stage 1 Output Swing (±10mV in) Min. Slew Rate (10kHz, 10Vpk out)
1 (Unity) Open (No R_G) 1.000 ±10 mV 0.63 V/µs
10 11.1 kΩ 9.991 ±100 mV 0.63 V/µs
100 1.00 kΩ 100.8 ±1.0 V 0.63 V/µs
1000 100 Ω 999.0 ±10.0 V (Rail Limit) 0.63 V/µs

For the op-amps themselves, the Texas Instruments OPA2277 is an excellent dual precision choice. It offers a typical offset voltage of 20µV, a slew rate of 0.8 V/µs, and low bias currents, making it ideal for the first stage where input impedance and DC precision are critical.

Behavior Matrix: What Changes When One Element Changes

Component Changed Direction of Change Effect on Circuit Behavior
R_G (Gain Resistor) Increases Overall differential gain decreases. Bandwidth increases slightly due to lower closed-loop gain.
R_F1 or R_F2 Increases (Unbalanced) Stage 1 becomes asymmetrical. Common-mode voltage at Node A and Node B diverges, severely degrading overall CMRR.
R_3 or R_5 (Stage 2 Input) Increases Stage 2 gain decreases. Input impedance of the subtractor stage drops, potentially loading down Stage 1 if driven too hard.
R_4 (Stage 2 Feedback) Increases Stage 2 gain increases. The subtraction ratio breaks, causing common-mode voltage to appear at V_OUT.

Why This Topology Over the Alternative

The primary alternative to the three-op-amp topology is the single-op-amp difference amplifier (four resistors and one op-amp). While cheaper and simpler, the single-op-amp difference amplifier fails in precision sensor applications for two fundamental reasons.

First, input impedance. In a single-op-amp difference amplifier, the input impedance is dictated by the input resistors (e.g., 10 kΩ). If you are measuring a thermocouple, a Wheatstone bridge, or a biomedical electrode, loading the sensor with 10 kΩ will cause massive measurement errors and signal attenuation. The three-op-amp topology routes the signals directly into the non-inverting inputs of U1 and U2, presenting input impedances in the Gigaohm range (limited only by the op-amp's common-mode input impedance and PCB leakage).

Second, CMRR vs. Gain trade-off. In a single-op-amp design, CMRR is entirely dependent on the physical matching of the four resistors. If you need a gain of 100, you must use a 1MΩ feedback resistor and a 10kΩ input resistor. Finding 0.01% matched resistors at 1MΩ is expensive and thermally unstable. In the three-op-amp topology, Stage 2 remains at unity gain (using easily matched 10kΩ arrays), while Stage 1 handles the high gain using standard, low-value precision resistors. As Stage 1 gain increases, the overall system CMRR actually improves, because the differential signal is amplified before the subtraction stage introduces its fixed common-mode error.

Failure Modes: What Breaks at the Extremes

When debugging a custom instrumentation amplifier on the bench, you must understand how the circuit fails when a component opens or shorts. Here is the exact failure-mode contrast for the critical nodes.

  • R_G Opens: The cross-feedback path between U1 and U2 is broken. The inverting inputs of U1 and U2 now only see their local feedback resistors tied to their own outputs. Both U1 and U2 revert to unity-gain voltage followers. The overall circuit gain drops to exactly 1.0 (assuming Stage 2 is unity). Diagnostic signature: V_OUT tracks V_IN+ minus V_IN- with no amplification.
  • R_G Shorts: The resistance between the two inverting inputs drops to zero. The Stage 1 gain formula approaches infinity. U1 and U2 will immediately saturate, slamming Node A and Node B to the positive or negative supply rails depending on the input offset voltage. Diagnostic signature: V_OUT is pegged to the supply rail; U1 and U2 draw maximum quiescent current and may overheat.
  • R_4 (Stage 2 Feedback) Opens: U3 loses negative feedback. The non-inverting input (driven by Node B) will force U3 to saturate to the positive rail. Diagnostic signature: V_OUT sits at +VCC minus the output stage voltage drop (typically ~1.5V for the OPA2277).
  • Stage 2 Resistor Drift (Mismatch): If R_6 drifts by just 0.5% relative to the other three 10kΩ resistors due to thermal gradients on the breadboard, the subtraction is no longer perfect. A 1V common-mode signal will leak through to the output as a 5mV error. Diagnostic signature: Injecting a common-mode AC signal (tying V_IN+ and V_IN- together) yields a visible sine wave on the oscilloscope at V_OUT instead of a flat line.

Step-by-Step Breadboard Testing and Debugging

Do not just wire up the circuit, apply power, and hope for the best. Follow this systematic verification sequence using a dual-channel oscilloscope and a precision digital multimeter (DMM).

  1. Verify Power and Decoupling: Before inserting the op-amps, set your bench power supply to ±12V. Measure the rails at the breadboard power buses with your DMM. Ensure the voltage is within ±100mV of 12.00V and that AC ripple is below 5mV RMS on the scope.
  2. Check Quiescent Current: Insert the OPA2277 ICs. With inputs grounded, measure the voltage drop across a 10Ω sense resistor placed in the +12V supply line. The OPA2277 draws roughly 750µA per amplifier. For three amplifiers (one dual, one single, or two duals with one half unused), expect roughly 2.25mA total. A reading >10mA indicates a short or oscillation.
  3. Null the Input Offset: Short V_IN+ and V_IN- to ground. Measure V_OUT with your DMM on the millivolt range. For a gain of 100, a 20µV input offset will yield a 2mV output offset. If the output is saturated, check for open feedback paths or a missing ground connection on R_6.
  4. Inject a Differential Signal: Use a function generator with a DC offset to apply +5mV to V_IN+ and -5mV to V_IN- (10mV differential). Verify V_OUT reads exactly 1.000V (for G=100). Swap the inputs; V_OUT should read -1.000V.
  5. Stress Test CMRR: Tie V_IN+ and V_IN- together. Connect the function generator to both inputs simultaneously. Inject a 1 kHz, 2V peak-to-peak sine wave. Probe V_OUT with the oscilloscope on AC coupling at 10mV/div. A well-matched Stage 2 will show a flat line. If you see a sine wave >5mV peak-to-peak, your Stage 2 resistors are mismatched. Swap them or use a monolithic matched resistor network (like the LT5400) for R_3, R_4, R_5, R_6.

Building a discrete instrumentation op amp circuit forces you to confront the physical realities of component tolerances and PCB layout that are hidden inside integrated instrumentation amps like the INA128. By mastering this topology, you gain the ability to customize bandwidth, filter specific noise frequencies between stages, and interface with extreme high-impedance sensors that off-the-shelf ICs cannot handle.