The Core Formulas and Topology Nodes
When you need to scale inductance or current handling without sourcing a custom magnetic component, combining off-the-shelf inductors is the standard bench workaround. The inductors in series and parallel formula behaves identically to resistors, provided one critical condition is met: mutual inductance ($M$) must be zero. This means the magnetic fields of the components must not interact. Physically, this requires spacing them at least one component-width apart or mounting them at 90-degree orthogonal angles.
Series Topology
In a series configuration, the output node of the first inductor feeds directly into the input node of the second.
- Node A (Input): Upstream voltage source or switching node.
- Node B (Junction): The electrical connection between L1 and L2. This node should be kept as physically short as possible to minimize parasitic trace inductance.
- Node C (Output): Downstream load or filter capacitor.
Formula: $L_{total} = L_1 + L_2 + ... + L_n$
Parallel Topology
In a parallel configuration, the input nodes of all inductors tie together, and the output nodes tie together.
- Node A (Input Split): Common input trace that branches to L1 and L2.
- Node B (Output Recombine): Common output trace where L1 and L2 merge.
Formula: $\frac{1}{L_{total}} = \frac{1}{L_1} + \frac{1}{L_2} + ... + \frac{1}{L_n}$
For two identical inductors in parallel, this simplifies to $L_{total} = \frac{L}{2}$. For a deeper theoretical breakdown of magnetic coupling and ideal assumptions, refer to the All About Circuits inductor guide.
Behavior Matrix: What Happens When One Inductor Fails?
Designing with multiple magnetics isn't just about hitting a target microhenry ($\mu H$) value; it's about understanding how the circuit degrades. A single large inductor represents a single point of failure. Splitting the inductance changes the failure mechanics entirely.
| Topology | Failure Mode | Electrical Result | Physical Consequence |
|---|---|---|---|
| Series | One inductor opens (wire break) | $L_{total}$ becomes infinite (open circuit). Current drops to zero. | Downstream load loses power. Safe failure, but system halts. |
| Series | One inductor shorts (insulation melt) | $L_{total}$ drops to the value of the remaining inductor(s). | Ripple current spikes. Downstream capacitor may overheat from excessive AC ripple. |
| Parallel | One branch opens | $L_{total}$ increases (recalculates without the open branch). | Remaining inductor(s) must carry 100% of the load current. High risk of core saturation and thermal runaway. |
| Parallel | One branch shorts | $L_{total}$ approaches zero. The entire parallel bank becomes a dead short. | Massive current spike. Will likely destroy the upstream switching MOSFET or blow the main input fuse. |
Design Walkthrough: Picking Real Values for a Buck Converter Filter
Let’s apply the inductors in series and parallel formula to a real-world power delivery problem. You are designing a 48V-to-12V synchronous buck converter using a TI TPS53513 controller. The datasheet and TI's inductor selection application note dictate you need a 5.0 $\mu H$ inductor capable of handling 22A RMS continuous current.
The Problem: A single 5.0 $\mu H$, 25A shielded power inductor (like the Würth Elektronik 7443552500) costs around $6.50, has a massive 13x13mm footprint, and creates a localized thermal hotspot on the PCB.
The Parallel Solution: Instead of one massive choke, we use two 10 $\mu H$ inductors in parallel.
- Calculate Inductance: $L_{total} = \frac{10 \mu H}{2} = 5.0 \mu H$. Target met.
- Select the Component: We choose the Coilcraft XEL1030-103 (10 $\mu H$, 14A saturation current, 10A RMS thermal rating). Cost: ~$1.30 each.
- Verify Current Splitting: 22A total / 2 branches = 11A per inductor. The XEL1030-103 is rated for 10A RMS thermal, which is slightly under. We need a slightly larger part. We swap to the Coilcraft XEL1040-103 (10 $\mu H$, 16A saturation, 13A RMS). 11A is well within the 13A thermal limit.
- Calculate DCR (DC Resistance): The XEL1040-103 has a max DCR of 1.8 m$\Omega$. Two in parallel yields an effective DCR of 0.9 m$\Omega$. This cuts $I^2R$ copper losses significantly compared to the single large inductor's 1.4 m$\Omega$ DCR.
- Physical Layout: Place L1 and L2 side-by-side but rotate one by 90 degrees. This orthogonal placement ensures the magnetic flux lines do not intersect, keeping mutual inductance ($M$) at zero and ensuring the math holds true.
Breadboard Testing Protocol: Step-by-Step Verification
Testing inductors on a solderless breadboard is notoriously tricky. Breadboard contacts introduce ~100 m$\Omega$ of contact resistance and ~2 pF of parasitic capacitance per row. If you use a cheap multimeter's basic inductance setting (which often tests at 1 kHz), your readings will be skewed. Power inductors must be tested at their operational switching frequency (typically 100 kHz to 1 MHz).
Follow this exact protocol to verify your series/parallel math on the bench:
- De-energize and Isolate: Ensure the breadboard is completely unpowered. Disconnect any capacitors or active ICs from the inductor nodes. Parallel capacitance will completely ruin an LCR meter's inductance reading.
- Zero the LCR Meter: Use a benchtop LCR meter (like a Keysight E4980A or a DER EE DE-5000). Short the test leads together and execute the 'Short Zero' calibration to null out the lead inductance (usually around 0.5 $\mu H$ of parasitic trace).
- Set Test Frequency: Configure the LCR meter to 100 kHz, 1 Vrms. This matches standard buck converter switching frequencies.
- Measure Individual Baselines: Probe L1 and L2 individually directly at the component leads (not the breadboard rails). Record the exact values (e.g., 9.8 $\mu H$ and 10.1 $\mu H$).
- Wire and Measure Series: Jumper Node B. Probe Node A and Node C. Verify the sum is $L_1 + L_2$. If the reading is higher than expected, your inductors are too close together and mutual inductance is adding to the total. Move them apart.
- Wire and Measure Parallel: Jumper the inputs to Node A and outputs to Node B. Probe across the bank. Verify the reading matches the reciprocal formula. If the reading is unstable, check for loose breadboard contacts causing one branch to drop out intermittently.
Decision Tree: Series vs. Parallel for Your Next Build
Stop guessing which topology to use. Use this decision matrix to terminate your design phase with a concrete component pick.
| Design Requirement | Topology Choice | Concrete Default Pick (2026) |
|---|---|---|
| High current DC-DC output filter (>5A) | Parallel | Coilcraft XEL or XPL series (Composite core, high saturation, low DCR) |
| Low-current EMI / Ferrite bead replacement (<1A) | Series | Murata LQH or LQM series (Multilayer chip inductors, high impedance) |
| Need to increase inductance without changing BOM footprint | Series | Wurth WE-LQS series (Shielded, tight coupling acceptable if designed for it) |
| Need to reduce thermal hotspot on a dense 4-layer PCB | Parallel | Taiyo Yuden CBC series (Distributed layout, excellent thermal dissipation) |
The Final Verdict
There is no 'it depends' when it comes to power electronics. If you are routing power (DC-DC converters, motor drives, battery management), default to parallel inductors. The reduction in DCR, the distribution of thermal load across the PCB, and the redundancy against single-point saturation make parallel the undisputed choice for high-current rails. If you are routing signals (RF chokes, snubber circuits, EMI filtering), default to series. Series topologies maximize impedance to high-frequency noise without adding the copper losses that plague parallel power designs. Pick your topology based on the current, not just the microhenry target.
