When combining inductors in parallel and series, the baseline math mirrors capacitors (the inverse of resistors). However, theoretical inductance ($L_{eq}$) is only half the battle. In real-world power electronics, parasitics like DC resistance (DCR), saturation current ($I_{sat}$), and self-resonant frequency (SRF) dictate which topology actually survives on the PCB. Choosing the wrong configuration doesn't just alter your filter cutoff; it guarantees a saturated core, a melted winding, or a blown downstream MOSFET.

This guide cuts through the textbook abstractions to show you exactly how these topologies behave under load, what breaks when they fail, and how to select real component values for your next power design.

Topology Definitions and Node Mapping

To analyze these circuits precisely, we must define our nodes. Assume current flows from an input source at Node A to a load at Node B.

  • Series Topology: Inductor L1 connects Node A to an intermediate Node X. Inductor L2 connects Node X to Node B. The same current flows through both components sequentially.
  • Parallel Topology: Both L1 and L2 connect directly between Node A and Node B. The total current splits between the two branches based on their impedance (which, at DC, is purely their DCR).

The theoretical inductance formulas are straightforward:

  • Series: $L_{eq} = L_1 + L_2$ (Assuming zero mutual coupling)
  • Parallel: $L_{eq} = \frac{L_1 \times L_2}{L_1 + L_2}$ (For two inductors)
Coupling Warning: These formulas assume the magnetic fields of the inductors do not interact. If you place two unshielded inductors physically close together on a PCB, mutual inductance ($M$) will alter the total inductance. Always use shielded inductors (like molded ferrite types) or maintain a minimum spacing of 2x the inductor diameter when combining them.

Behavior Matrix: How Real Parameters Shift

Theoretical inductance is useless if the inductor saturates or overheats. Here is how the critical physical parameters change when you combine identical inductors (each with inductance $L$, DC resistance $R$, and saturation current $I_{sat}$).

Parameter Series (2x Identical) Parallel (2x Identical) Engineering Impact
Total Inductance $2L$ $0.5L$ Series increases filtering; parallel decreases it.
Total DCR $2R$ $0.5R$ Parallel halves $I^2R$ copper losses, critical for high-current rails.
Saturation Current ($I_{sat}$) $1 \times I_{sat}$ (Limited by weakest link) $2 \times I_{sat}$ Parallel doubles the current handling before core saturation.
Self-Resonant Freq (SRF) Decreases (Parasitic C adds) Increases (Parasitic C halves) Parallel is superior for high-frequency switching converters (e.g., >1MHz).

As highlighted by design tools like the Würth Elektronik REDEXPERT platform, AC core losses also shift dramatically. In parallel, the ripple current splits, keeping each core deeper in its linear region and drastically reducing total hysteresis losses.

Failure Modes at the Extremes: Opens and Shorts

Inductors fail primarily by opening (wire bond breaks) or shorting (insulation breakdown between windings). The topology determines whether a failure is a graceful degradation or a catastrophic chain reaction.

Series Topology Failures

  • One Inductor Opens: The entire circuit opens. Current stops flowing to the load. This is a safe failure mode for the downstream silicon, though the load loses power.
  • One Inductor Shorts: Total inductance drops to the value of the surviving inductor. The ripple current increases. If the surviving inductor was not sized to handle the full peak current alone, it will saturate, potentially leading to a secondary short.

Parallel Topology Failures

  • One Inductor Opens: Total inductance doubles. The surviving inductor is now forced to carry 100% of the load and ripple current. Because it was originally sized for 50% of the load, it will almost certainly hit $I_{sat}$, turn into a low-resistance wire, and pass massive current spikes to the output capacitor and load.
  • One Inductor Shorts: Total inductance drops to near zero. The switching node sees a direct short to the output during the MOSFET's ON-time. This results in immediate, catastrophic overcurrent destruction of the switching MOSFET.
Design Rule: Because parallel inductors hide single-point failures until they cascade, always design parallel inductor branches with individual overcurrent protection, or ensure the upstream controller has a fast, cycle-by-cycle current limit that can detect the sudden rise in $di/dt$ if one branch opens.

Design Walkthrough: Sizing a 5A LED Driver Filter

Let’s apply this to a concrete design problem. You are building a buck-converter-based LED driver that requires 50µH of inductance and must handle 5A of continuous RMS current with minimal thermal rise.

Option A: Single Inductor
You look for a single 50µH, 6A inductor. You find the Bourns SRP1265A-500M. It meets the specs, but its DCR is 68mΩ. At 5A, copper loss is $I^2R = 25 \times 0.068 = 1.7W$. In a compact, unventilated LED housing, 1.7W of localized heat will degrade the component's lifespan.

Option B: Series Topology
You use two 25µH inductors in series. The DCR adds up. If each has 35mΩ DCR, total DCR is 70mΩ. You gain no thermal advantage, and you consume twice the PCB footprint. Discard this option.

Option C: Parallel Topology (The Winner)
You select two Bourns SRP1265A-101M (100µH, 2.8A $I_{rms}$, 130mΩ DCR) inductors in parallel.
- Total Inductance: $100µH / 2 = 50µH$. (Target met).
- Total Current Handling: $2.8A \times 2 = 5.6A$. (Target met with 12% margin).
- Total DCR: $130mΩ / 2 = 65mΩ$.
- Copper Loss: $25 \times 0.065 = 1.625W$ total, but crucially, this heat is distributed across two physical footprints, cutting the thermal density in half. Furthermore, standard 100µH inductors are often cheaper and more readily available than niche 50µH high-current variants.

For a comprehensive look at calculating these ripple currents and selecting the right core material, refer to the Texas Instruments inductor selection application note (SLVA371), which details the relationship between ripple ratio and core saturation.

Breadboard Verification: Step-by-Step Testing

Before committing to a PCB layout, verify your parallel/series math on a breadboard. Note that breadboards introduce parasitic resistance (often 0.1Ω to 0.5Ω per contact), which will skew DCR measurements. Use thick, short jumper wires.

  1. Configure the LCR Meter: Set your LCR meter (e.g., Keysight U1733C or a DER EE DE-5000) to measure inductance ($L$) at 100kHz. (Testing at 1kHz is useless for switching power supply inductors, as core permeability shifts with frequency).
  2. Zero the Leads: Short the test probes together and press the "Zero" or "CAL" button to null out the lead inductance (usually 1-2µH of parasitic wire inductance).
  3. Baseline Measurement: Measure L1 and L2 individually. Record both $L$ and DCR (switch meter to DC resistance mode for DCR).
  4. Series Test: Connect L1's output pin to L2's input pin (Node X). Probe Node A and Node B. Verify the reading is $L_1 + L_2 \pm 10\%$.
  5. Parallel Test: Connect both L1 and L2 inputs to Node A, and both outputs to Node B. Probe across the nodes. Verify the reading is $(L_1 \times L_2) / (L_1 + L_2) \pm 10\%$.
  6. DCR Check: Switch the multimeter to the milliohm range. Measure the parallel DCR. If your meter lacks the resolution to read sub-100mΩ accurately, inject a known 1A DC current through the parallel pair and measure the voltage drop ($R = V/I$) to calculate the true DCR.

The Final Decision Tree: Which Topology Wins?

Do not default to a single oversized inductor without checking the parallel math first. Use this decision matrix to finalize your BOM.

Design Constraint Choose Series When... Choose Parallel When...
Current / Thermal Load is < 1A and thermal density is not a concern. Load is > 3A and you need to distribute $I^2R$ heat across the PCB.
Inductance Value You need a high, non-standard $L$ value and only have smaller standard values in stock. You need a low $L$ value but require high current handling (e.g., 2µH at 20A).
Voltage Isolation Operating in high-voltage strings where winding-to-winding voltage limits require splitting the potential. Operating in standard low-voltage DC-DC converters (under 60V).
High Frequency (SRF) Switching frequency is low (< 200kHz). Switching frequency is high (> 1MHz) and you need to push the SRF higher.

The Default Recommendation: For modern, high-efficiency DC-DC buck converters and LED drivers operating above 2A, inductors in parallel is the superior topology. It halves DCR, doubles current capacity, distributes thermal loads, and improves SRF. If your design requires 10µH at 15A, do not buy a single massive, expensive 15A choke. Instead, specify two Coilcraft XGL6060-223 (22µH, 8.4A) inductors in parallel, yielding 11µH at 16.8A with a fraction of the thermal footprint.