When off-the-shelf inductors don't match your exact target inductance or current rating, combining them is a standard bench and production workaround. However, unlike resistors, inductors introduce magnetic coupling, saturation limits, and complex failure cascades. The direct rule for inductor series parallel configurations is simple: series connections add inductance ($L_{total} = L_1 + L_2$) while parallel connections reduce it ($L_{total} = \frac{L_1 \times L_2}{L_1 + L_2}$), assuming zero mutual inductance. But in physical hardware, DC resistance (DCR), saturation current ($I_{sat}$), and magnetic coupling dictate whether your circuit survives the first power cycle.
The Core Topology: Nodes, Labels, and Equivalent Inductance
To analyze these configurations, we define our nodes. In a series topology, current flows from the source into Node A (Input), through $L_1$ to Node B (Junction), through $L_2$, and out to Node C (Output/Load). In a parallel topology, both $L_1$ and $L_2$ share Node A at their input terminals and Node B at their output terminals.
The table below maps standard E12/E24 inductor values to their resulting series and parallel equivalents, including the combined DC resistance (DCR) assuming typical wirewound power inductors. This data is critical for calculating $I^2R$ copper losses in switching converters.
| L1 (µH) | L2 (µH) | Series Total (µH) | Parallel Total (µH) | Typical L1 DCR (mΩ) | Typical L2 DCR (mΩ) | Series DCR (mΩ) | Parallel DCR (mΩ) |
|---|---|---|---|---|---|---|---|
| 10 | 10 | 20.0 | 5.0 | 14.5 | 14.5 | 29.0 | 7.25 |
| 10 | 22 | 32.0 | 6.88 | 14.5 | 28.0 | 42.5 | 9.56 |
| 22 | 47 | 69.0 | 14.98 | 28.0 | 45.0 | 73.0 | 17.24 |
| 47 | 100 | 147.0 | 31.98 | 45.0 | 72.0 | 117.0 | 27.69 |
Series vs. Parallel: When to Use Which Topology
Choosing between series and parallel isn't just about hitting a target microhenry value; it's about managing thermal limits and high-frequency impedance. Here is the decision framework for selecting the right topology.
| Criteria | Series Configuration | Parallel Configuration |
|---|---|---|
| Primary Use Case | Achieving high inductance; multi-stage EMI filtering. | High-current delivery; reducing overall DCR and thermal load. |
| Saturation Current ($I_{sat}$) | Limited by the lowest $I_{sat}$ in the chain. | Increases (current splits, assuming matched DCR). |
| DC Resistance (DCR) | Additive (increases copper loss and heat). | Reduces (lowers copper loss and improves efficiency). |
| Physical Footprint | Requires board length; routing can be tricky. | Requires board width; easier to place near switch nodes. |
| Mutual Inductance Risk | High if placed close; can cause unexpected impedance spikes. | High if placed close; can cause current imbalance. |
Use series when you need to block high-frequency noise. For example, placing a 10µH power inductor in series with a 600Ω ferrite bead creates a two-stage low-pass filter that stops both switching ripple and high-frequency RF. Use parallel when your switching regulator demands 15A, but the only inductors that fit your footprint max out at 10A. Paralleling two 10A inductors shares the thermal burden, provided their DCRs are tightly matched.
Extreme Failure Modes: What Breaks When an Inductor Fails?
Inductors rarely fail silently. Wirewound components typically fail open due to thermal overstress melting the internal bond wire, or they fail shorted due to insulation breakdown between windings. Understanding the failure cascade is mandatory for reliable power supply design.
Series Topology Failures
- One Inductor Opens: The entire circuit breaks. Current drops to zero. In a buck converter, this results in an immediate loss of output voltage. The controller will likely latch off or hiccup, but no catastrophic damage occurs to the switching FET.
- One Inductor Shorts: The total inductance drops to the value of the surviving inductor. The DCR drops. The controller may experience higher peak-to-peak ripple current, and the surviving inductor may overheat due to the unexpected increase in AC ripple flux, but the system often continues to operate in a degraded state.
Parallel Topology Failures
- One Inductor Opens: This is the most dangerous failure mode. 100% of the load current instantly shifts to the surviving inductor. If the surviving inductor's $I_{sat}$ is lower than the total load current, its core saturates. Its inductance collapses to near-zero, causing a massive current spike that will almost certainly destroy the high-side MOSFET and potentially the controller IC.
- One Inductor Shorts: The total inductance collapses to near-zero. The shorted inductor acts as a dead short across the switch node to ground (or output), causing immediate overcurrent protection (OCP) tripping or catastrophic FET failure.
Design Walkthrough: Sizing Real Inductors for a High-Current Filter
Let's design the output filter for a 5V-to-3.3V synchronous buck converter delivering 12A continuous current. The controller datasheet recommends a 4.7µH inductor. However, searching distributor catalogs for a single 4.7µH inductor with a 15A $I_{sat}$ (allowing 20% ripple margin) yields massive, expensive components like the Bourns SRP1265A series in large footprints.
The Parallel Solution:
Instead of one massive inductor, we parallel two Bourns SRP1265A-100M inductors.
- Specs per unit: 10µH, 11A $I_{sat}$, 14.5mΩ DCR.
- Combined Inductance: $\frac{10 \times 10}{10 + 10} = 5.0µH$. (5.0µH is close enough to 4.7µH; the slightly higher inductance will just reduce the ripple current slightly, which is beneficial).
- Combined DCR: $\frac{14.5}{2} = 7.25mΩ$.
- Current Splitting: At 12A total load, each inductor carries 6A of DC current. This is well below the 11A $I_{sat}$ limit, keeping the core out of saturation and drastically reducing $I^2R$ heating compared to a single smaller inductor pushed to its limits.
To prevent mutual inductance from skewing our 5.0µH target, we must place the two SRP1265A inductors at least 5mm apart and rotate one 90 degrees relative to the other. Because the SRP1265A is a shielded core part, cross-coupling is minimal, but physical rotation guarantees the magnetic flux lines intersect orthogonally, driving the coupling coefficient ($k$) effectively to zero.
Breadboard Testing: Step-by-Step Verification
Before committing a parallel or series inductor network to a custom PCB, validate the math on the bench. You will need an LCR meter (like the DER EE DE-5000 or a Keysight U1733C), your inductors, and a solderless breadboard. Note that breadboard parasitic capacitance can skew readings above 100kHz, so stick to the standard 1kHz or 10kHz test frequency for baseline validation.
- Zero the Probes: Short the LCR meter probes together and execute the 'Zero' or 'Relative' function to null out the probe resistance and inductance (usually around 0.2µH and 50mΩ).
- Measure Individual Baselines: Measure $L_1$ and $L_2$ individually at 1kHz. Record both the inductance ($L_s$) and the series resistance ($R_s$, which represents DCR). Write these on the component tape.
- Wire the Topology: Plug the inductors into the breadboard. For series, use a short jumper to link the output of $L_1$ to the input of $L_2$. For parallel, use jumpers to tie both inputs to a common rail and both outputs to another common rail.
- Measure Combined Value: Probe the outer nodes (Node A and Node C for series; Node A and Node B for parallel). Compare the reading to your calculated target. If the measured value is more than 5% off from the theoretical calculation, mutual inductance is at play.
- The Rotation Test (Crucial): If your parallel measurement reads 5.8µH instead of the expected 5.0µH, the magnetic fields are coupling constructively. Pull one inductor out, rotate it 90 degrees, and re-measure. You should see the value drop back to the theoretical 5.0µH. This confirms your physical layout strategy for the final PCB.
- Verify DCR Scaling: Switch the LCR meter to DC resistance mode. Verify that the series DCR is the sum of the parts, and the parallel DCR follows the reciprocal formula. If parallel DCR is higher than expected, check for poor breadboard contact resistance, which can easily add 50mΩ to low-resistance power inductors.
By treating inductor series parallel configurations as a thermal and magnetic design challenge rather than just a simple math equation, you ensure your power stages remain stable, efficient, and protected against catastrophic single-point failures. Always consult component datasheets for $I_{sat}$ derating curves at elevated temperatures, as a 10A inductor at 25°C might only handle 7A inside a 60°C enclosure.
