When you need a specific inductance or current rating that isn't available in a single off-the-shelf footprint, combining an inductor in series and parallel configurations is a standard bench and production workaround. While the math mirrors resistors—series adds inductance, parallel reduces it—the real-world physics involving DC resistance (DCR), saturation current ($I_{sat}$), and parasitic capacitance dictate whether your circuit will filter cleanly or trigger a thermal shutdown.
This guide skips the abstract textbook theory and goes straight into node-level topology behavior, a real-world buck converter design walkthrough using specific Bourns part numbers, failure-mode contrasts, and exact steps to verify your network on the bench.
Core Topology and Node Behavior
Before dropping components onto a PCB, we must define the nodes. Assume a signal or power flow entering at Node A and exiting at Node C.
- Series Topology: Current flows from Node A through Inductor 1 (L1) to Node B, then through Inductor 2 (L2) to Node C. The total inductance is the sum ($L_{eq} = L_1 + L_2$), and the total DCR is the sum ($R_{eq} = R_1 + R_2$). The saturation current limit is dictated by the weakest inductor in the chain.
- Parallel Topology: Node A splits into two branches, one through L1 and one through L2, recombining at Node C. The total inductance follows the reciprocal rule ($1/L_{eq} = 1/L_1 + 1/L_2$). The DCR halves (if matched), and the current handling capacity adds up.
Note: All calculations below assume mutual inductance ($M$) is zero. This requires using magnetically shielded inductors or placing unshielded parts at least one component-width apart on orthogonal axes.
| Configuration | Total Inductance | Total DCR | Current Limit ($I_{sat}$) | If L1 Fails OPEN | If L1 Fails SHORT |
|---|---|---|---|---|---|
| Series (L1 + L2) | $L_1 + L_2$ | $R_1 + R_2$ | Min($I_{sat1}$, $I_{sat2}$) | Circuit breaks; $I = 0$ | $L_{eq}$ drops to $L_2$; $I$ spikes |
| Parallel (L1 || L2) | $(L_1 \times L_2) / (L_1 + L_2)$ | $(R_1 \times R_2) / (R_1 + R_2)$ | $I_{sat1} + I_{sat2}$ (approx) | $L_{eq}$ jumps to $L_2$; L2 saturates | $L_{eq}$ drops to ~0; massive $I$ spike |
| Series (Matched) | $2L$ | $2R$ | $I_{sat}$ | Safe fail (open circuit) | Inductance halves; ripple increases |
| Parallel (Matched) | $L / 2$ | $R / 2$ | $2 \times I_{sat}$ | Thermal runaway risk on L2 | Catastrophic upstream FET failure |
Real-World Design Walkthrough: The Parallel Current-Boost Trick
Why choose a parallel inductor topology over a single large component or a series chain? Series configurations are primarily used in EMI filtering (e.g., pi-filters) to maximize impedance at high frequencies without saturating. Parallel configurations are used in power delivery—specifically DC-DC buck converters—when you need high current handling in a constrained PCB footprint.
Let's design an output filter for a 5V/3A synchronous buck converter. The controller requires a 7.5µH inductor capable of handling 3.2A RMS without exceeding a 40°C temperature rise.
The Problem: Looking at the popular Bourns SRN6045TA series (6x6mm footprint, 4.5mm height), the 6.8µH part (SRN6045TA-6R8M) is only rated for 2.2A. The next size up in the same family that handles 3A+ requires moving to an 8x8mm footprint (SRN8040TA), which violates our mechanical constraints.
The Solution: We place two 15µH inductors (SRN6045TA-150M) in parallel.
- Target Inductance: $15\mu H / 2 = 7.5\mu H$ (Perfect match for the controller).
- Current Handling: The SRN6045TA-150M has an $I_{rms}$ of 1.6A. Two in parallel yield $1.6A + 1.6A = 3.2A$.
- DCR Reduction: A single 15µH part has a DCR of 68mΩ. In parallel, the effective DCR drops to 34mΩ, cutting $I^2R$ conduction losses by half compared to a single equivalent part.
- Footprint: Two 6x6mm parts easily fit within the area of a single 12x12mm high-current inductor, and they can be placed on opposite sides of the PCB if thermal dissipation is a concern.
In parallel topologies, current does not split perfectly 50/50 unless the DCR and PCB trace lengths are identical. A 5mΩ difference in trace resistance can skew current sharing by 10-15% at high loads. Always route symmetrical, matched-length copper pours from the switching node to the inductor pads to ensure balanced thermal loading.
Failure Mode Contrast: What Breaks at the Extremes?
Understanding how an inductor network fails is just as critical as knowing how it operates. The fault tolerance of series versus parallel topologies is fundamentally different.
Series Topology Failures
If an inductor in series fails open (e.g., the internal wire bond snaps due to mechanical shock), the entire circuit stops functioning. In a power supply, this is a 'safe fail'—the output drops to zero, but no downstream components are overvolted. If it fails short (rare, but possible if insulation breaks down and turns melt together), the total inductance drops. In a buck converter, this increases the inductor ripple current, potentially triggering the controller's over-current protection (OCP) or causing excessive output voltage ripple.
Parallel Topology Failures
Parallel networks carry a hidden danger. If L1 fails open, the total inductance instantly doubles (jumping from 7.5µH to 15µH in our design example). While higher inductance sounds harmless, the remaining inductor (L2) is now forced to carry 100% of the load current. Since L2 was only sized for 50% of the load, it will rapidly hit its saturation current ($I_{sat}$). Once saturated, the inductor acts like a short piece of wire, current spikes massively, and L2 will thermally destroy itself or blow the upstream MOSFET.
If L1 fails short, the total inductance collapses toward zero. The switching node is effectively shorted to the output capacitor during the on-time, resulting in instantaneous, catastrophic failure of the high-side switch.
Bench Verification: Breadboard Testing Step-by-Step
Never trust the datasheet value blindly when prototyping. Parasitic capacitance from breadboard contacts and jumper wires alters the Self-Resonant Frequency (SRF) of the inductor network. Here is how to validate your series or parallel inductor topology on the bench using an LCR meter (like the DER EE DE-5000 or Keysight U1733C) and an oscilloscope.
Step 1: Verify DCR with a Multimeter
Before applying power, measure the DC resistance. For our parallel Bourns design, you should read approximately 34mΩ. Warning: Standard breadboard contacts add 10mΩ to 30mΩ of contact resistance. For accurate DCR measurement, solder the inductors to a scrap piece of copper-clad FR4 and use Kelvin (4-wire) clips.
Step 2: Measure Inductance at the Correct Frequency
Most cheap LCR meters default to 1kHz or 120Hz. Power inductors used in switching regulators operate at 500kHz to 2MHz. Set your LCR meter to 100kHz. Measure the parallel network; you should see ~7.5µH. If you measure significantly less, your inductors are too close together and mutual inductance is coupling the magnetic fields. Move them at least 10mm apart.
Step 3: Ringing Test for SRF Validation
Inductors have parasitic parallel capacitance. When combined with breadboard stray capacitance (~3pF per node), the SRF drops.
- Connect a function generator to Node A, outputting a 100kHz square wave (0V to 3.3V).
- Connect your oscilloscope probe (set to 10x to minimize probe capacitance) to Node C.
- Terminate Node C to ground with a 50Ω resistor to prevent infinite ringing.
- Look at the rising edge of the square wave on the scope. You will see a high-frequency 'ringing' or oscillation superimposed on the edge.
- Measure the period of that ringing. The inverse of that period is your actual SRF in the circuit. Ensure this SRF is at least 10x higher than your switching frequency to avoid impedance collapse.
For deeper reading on magnetics selection in switching regulators, the Analog Devices inductor selection guide provides excellent derivations on core loss versus copper loss trade-offs when scaling inductor networks. Additionally, the All About Circuits textbook chapter on inductors remains the definitive primer on the foundational math governing these topologies.
By treating inductor networks not just as mathematical abstractions but as physical components with thermal limits, DCR penalties, and specific failure modes, you can reliably engineer around supply chain shortages or footprint constraints without sacrificing power integrity.
