The fundamental inductor and capacitor equations governing transient circuit behavior are V = L × (ΔI / Δt) and I = C × (ΔV / Δt). These formulas dictate how energy storage components resist changes in current and voltage, forming the backbone of power supply design, filtering, and decoupling networks. If you are sizing a buck converter inductor or calculating the bulk capacitance needed to prevent an ESP32 brownout during a WiFi transmission spike, these are the exact equations you need.

The Core Inductor and Capacitor Equations Defined

Before plugging in numbers, we must define the physics. An inductor acts like a heavy water wheel in a pipe: it resists sudden changes in water flow (current). A capacitor acts like a pressurized accumulator tank: it resists sudden changes in water pressure (voltage). In electrical terms, the ideal transient equations are:

  • Inductor: VL = L × (ΔI / Δt)
  • Capacitor: IC = C × (ΔV / Δt)
SymbolVariableStandard UnitDefinition & Context
VLVoltage across inductorVolts (V)The potential difference driving the current change.
LInductanceHenries (H)The component's ability to store energy in a magnetic field.
ΔIChange in currentAmperes (A)The peak-to-peak ripple or transient current step.
ΔtTime intervalSeconds (s)The duration of the switching on-time or transient spike.
ICCurrent through capacitorAmperes (A)The charge/discharge current flowing into or out of the cap.
CCapacitanceFarads (F)The component's ability to store energy in an electric field.
ΔVChange in voltageVolts (V)The allowable voltage droop, ripple, or spike.
When These Apply (and Assumptions): These linear approximations assume an ideal component (zero DCR for inductors, zero ESR/ESL for capacitors) and a constant ramp rate (linear di/dt or dv/dt). They apply perfectly to the steady-state switching phases of DC-DC converters and short-duration digital logic transients. They break down if the inductor core saturates (inductance drops to near zero) or if the capacitor's dielectric absorption dominates over long timeframes.

Rearranged Forms for Component Sizing

In practical bench work, you rarely solve for voltage or current; you are solving for the physical component value required to meet a design constraint. Here are the rearranged forms you will use 95% of the time:

  • Solve for Inductance: L = VL × (Δt / ΔI) (Used to find the minimum uH to limit ripple current)
  • Solve for Inductor Ripple: ΔI = VL × (Δt / L) (Used to verify thermal limits and core saturation)
  • Solve for Capacitance: C = IC × (Δt / ΔV) (Used to size bulk decoupling to prevent brownouts)
  • Solve for Voltage Droop: ΔV = IC × (Δt / C) (Used to verify if a known capacitor will hold up the rail)
  • Solve for Hold-up Time: Δt = C × (ΔV / IC) (Used to calculate ride-through time during a power drop)

Unit Traps and Realistic Answer Magnitudes

The most common reason a calculated design fails on the bench is the 'prefix trap'. The standard equations demand base SI units: Henries, Farads, Amperes, Volts, and Seconds. Datasheets and schematics, however, use micro, milli, and nano prefixes.

The Multiplier Trap

If your switching frequency is 500 kHz, your time step is not 500; it is 2 × 10-6 seconds. If your target capacitance is 100 µF, you must enter 100 × 10-6 (or 0.0001) into the equation. Forgetting the 10-6 multiplier on a microhenry inductor calculation will result in a mathematically correct but physically impossible answer that is off by a factor of one million.

Realistic Magnitude Check

Always sanity-check your final answer against real-world component ranges. If your calculation yields a value outside these bounds, you have a unit error or a flawed design assumption:

  • Power Inductors (DC-DC): Typically 1 µH to 100 µH. (If you calculate 5 H, you are designing an electromagnet, not a buck converter).
  • RF/High-Speed Inductors: 1 nH to 500 nH.
  • Ceramic Decoupling Capacitors (MLCC): 100 pF to 100 µF.
  • Bulk Electrolytic/Polymer Capacitors: 10 µF to 10,000 µF (or 10 mF).

Worked Example 1: Sizing a Buck Converter Inductor

Scenario: You are designing a 12V-to-3.3V buck converter running at a switching frequency (fsw) of 500 kHz. The maximum load current is 2A, and you want to limit the inductor ripple current (ΔI) to 30% of the max load (0.6A peak-to-peak). What inductance do you need?

  1. Identify the Inductor Voltage (VL): During the switch ON-time, the voltage across the inductor is Vin - Vout.
    VL = 12V - 3.3V = 8.7V
  2. Calculate the ON-time (Δt): First, find the duty cycle D = Vout / Vin = 3.3 / 12 = 0.275.
    Δt = D / fsw = 0.275 / 500,000 Hz = 5.5 × 10-7 seconds (or 550 ns).
  3. Apply the Rearranged Inductor Equation:
    L = VL × (Δt / ΔI)
    L = 8.7 × (5.5 × 10-7 / 0.6)
  4. Track Units and Solve:
    L = 8.7 × (9.166 × 10-7) = 7.97 × 10-6 Henries
  5. Convert to Standard Prefix:
    7.97 × 10-6 H = 7.97 µH.

Verification: 7.97 µH falls perfectly in the realistic 1-100 µH range. In practice, you would select the next standard value up, which is 8.2 µH or 10 µH, ensuring the saturation current rating (Isat) exceeds the peak current (2A + 0.3A = 2.3A).

Worked Example 2: Sizing an ESP32 Bulk Decoupling Capacitor

Scenario: An ESP32-WROOM-32 module draws a transient current spike of 250 mA (0.25 A) for 150 µs (1.5 × 10-4 s) when transmitting on WiFi. The 3.3V rail is supplied by an LDO that cannot respond fast enough to this transient. You can tolerate a maximum voltage droop (ΔV) of 0.15V before the module resets. What bulk capacitance is required?

  1. Identify the Knowns in Base Units:
    IC = 0.25 A
    Δt = 1.5 × 10-4 s
    ΔV = 0.15 V
  2. Apply the Rearranged Capacitor Equation:
    C = IC × (Δt / ΔV)
    C = 0.25 × (1.5 × 10-4 / 0.15)
  3. Track Units and Solve:
    C = 0.25 × (0.001) = 0.00025 Farads
  4. Convert to Standard Prefix:
    0.00025 F = 250 µF.

Verification: 250 µF is a realistic bulk value. However, because electrolytic and tantalum capacitors have high Equivalent Series Resistance (ESR), the actual voltage droop will include an ESR component (Vdroop_total = ΔVcap + I × ESR). Therefore, you must select a low-ESR polymer capacitor or parallel this bulk cap with several 10 µF X5R MLCCs placed physically adjacent to the ESP32 VCC pin to handle the high-frequency di/dt edge.

Decision Tree: Selecting Your Physical Component

Equations give you the theoretical value; physics and supply chains dictate the physical part. Use this decision path to terminate your design with a concrete component selection.

Calculated RequirementApplication ContextComponent TechnologyConcrete Part Pick (2026)
L = 8.2 µH, Isat > 3A DC-DC Buck Converter (High efficiency, low EMI) Shielded Ferrite Core Power Inductor Würth Elektronik 744774210 (10 µH, 3.2A Isat, shielded to prevent crosstalk in dense RF layouts).
L = 47 nH, Isat > 500mA RF Matching Network / VHF Filter Multilayer Ceramic Chip Inductor Murata LQG15HN47NJ02 (47 nH, 0402 package, high Q-factor for minimal signal loss).
C = 250 µF, Vrated ≥ 6.3V, Low ESR MCU Bulk Decoupling (WiFi/BLE TX spikes) Solid Polymer Tantalum Capacitor Panasonic 6TPE220MAZB (220 µF, 6.3V, POSCAP series, ultra-low ESR of 15mΩ to minimize I×ESR droop).
C = 10 µF, Vrated ≥ 10V, High Frequency High-speed digital rail bypassing (FPGA/SoC) X7R Multilayer Ceramic Capacitor (MLCC) Samsung Electro-Mechanics CL21B106KOQNNNE (10 µF, 16V, 0805 X7R, low ESL for fast transient response).
Default Recommendation: If your inductor calculation lands between standard E12 values, always round up to the next available inductance to guarantee your ripple current stays below the calculated threshold. If your bulk capacitor calculation lands near a standard value, round up and prioritize a low-ESR polymer chemistry over a standard wet electrolytic to ensure the math holds true under high-frequency transient loads.

References and Further Reading

For deeper dives into the non-ideal behaviors (like inductor core saturation curves and capacitor dielectric absorption) that modify these ideal equations, consult the following authoritative resources: